DM9008F View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008F' PDF : 68 Pages View PDF
Remote Read Timing
1) The DMA reads a byte/word from local buffer memory
and writes the byte/word into the latch, increments the
DMA address, and decrements the byte count
(RBCR0, 1).
2) If the byte from local buffer memory is not available,
IOCHRDY will be pulled low to insert wait states to the
PC. The IOCHRDY is inactive when the byte is
available.
3) When the system reads the port, the read strobe
( IOR ) is used as an acknowledge by the remote
DMA.
Steps 1-3 are repeated until the remote DMA is finished.
Note that if a local DMA is in progress, the remote DMA is held
off until the local DMA is finished.
Remote Write Timing
A Remote Write operation transfers data from the I/O port to
the local buffer RAM. The system transfers a byte/word to the
latch via IOW , and this write strobe is detected by the ENC.
The remote DMA then holds off further transfers into the latch
until the current byte/word has been transferred from the latch,
after which the next transfer can begin.
1) The system writes a byte/word into the latch. If
DM9008 is not ready to accept the byte/word,
IOCHRDY will be pulled low to insert wait states into
the PC. IOCHRDY is inactive when the byte/word is
accepted by DM9008.
2) The remote DMA reads the contents of the port and
writes the byte/word to local buffer memory,
increments the address, and decrements the byte
count (RBCR0, 1).
Steps 1-2 are repeated until the remote DMA is finished.
DM9008
ISA/Plug & Play Super Ethernet Contoller
Slave Mode Timing
When the PC reads or writes any internal registers of DM9008,
DM9008 becomes a bus slave. All register accesses are
byte-wide. The PC accesses internal registers with four
address lines, SA0-SA3, and IOR and IOW strobes. Since
DM9008 may be a local bus master when the PC attempts to
read or write to DM9008, or attempts to read Boot-ROM data,
IOCHRDY will be pulled low to hold off the PC until DM9008
leaves master mode.
Boot-ROM Data Read
The Boot-ROM data pins are connected to Memory Data pins
MD0-7. DM9008 transfers these data to SD0-7 if the PC
activates a memory read operation with the address in the
range of the Boot-ROM address space.
Hardware Reset
DM9008 will be reset if RST is high. The ENC module can also
be reset when the PC reads the RESET port, followed by an
IOW operation.
The following bits will be cleared or set when DM9008 is reset.
Register
CR
ISR
IMR
DCR
TCR
Reset Bits
TXP, STA
D0 - D6
LB1, LB0
Set Bits
RD2, STP
RST
LAS
46
Final
Version: DM9008-DS-F02
November 30, 2000
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