DS3231MZ View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
'DS3231MZ' PDF : 20 Pages View PDF
±5ppm, I2C Real-Time Clock
Temperature Register (Upper Byte = 11h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT 5
DATA
0
Temperature Register (Lower Byte = 12h)
BIT 7
DATA
0
BIT 6
DATA
0
BIT 5
0
0
Temperature Registers (11h-12h)
BIT 4
DATA
0
BIT 3
DATA
0
BIT 2
DATA
0
BIT 1
DATA
0
BIT 0
DATA
0
BIT 4
0
0
BIT 3
0
0
BIT 2
0
0
BIT 1
0
0
BIT 0
0
0
Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and 12h. The tem-
perature is encoded in two’s complement format. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits,
the fractional portion, are at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the registers are set to
a default temperature of 0°C and the controller starts a temperature conversion. The temperature is read upon initial applica-
tion of VCC or I2C access on VBAT and once every second afterwards with VCC power or once every 10s with VBAT power. The
Temperature registers are also updated after each user-initiated conversion and are read only.
I2C Serial Port Operation
I2C Slave Address
The device’s slave address byte is D0h. The first byte
sent to the device includes the device identifier, device
address, and the R/W bit (Figure 8). The device address
sent by the I2C master must match the address assigned
to the device.
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
MSB
LSB
1 1 0 1 0 0 0 R/W
DEVICE
IDENTIFIER
READ/
WRITE BIT
Figure 8. I2C Slave Address Byte
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are
inactive and in their logic-high states. When the bus
is idle, it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued iden-
tically to a normal START condition. See Figure 1 for
applicable timing.
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