DS3231MZ View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

DS3231MZ

±5ppm, I2C Real-Time Clock

Maxim Integrated 

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±5ppm, I2C Real-Time Clock

TYPICAL I2C WRITE TRANSACTION

MSB

LSB

MSB

LSB

MSB

LSB

START

1

1

0

1

0

0

0

R/W

SLAVE

ACK

b7

b6

b5

b4

b3

b2

b1

b0

SLAVE

ACK

b7 b6 b5 b4 b3 b2 b1 b0

SLAVE

ACK

STOP

SLAVE

READ/

REGISTER ADDRESS

DATA

ADDRESS

WRITE

EXAMPLE I2C TRANSACTIONS

A) SINGLE BYTE WRITE

-WRITE CONTROL REGISTER

TO 44h

B) SINGLE BYTE READ

-READ CONTROL REGISTER

D0h

0Eh

44h

START

11010000

SLAVE

ACK

00001110

SLAVE

ACK

01000100

SLAVE

ACK

STOP

D0h

0Eh

START

11010000

SLAVE

ACK

00001110

SLAVE

ACK

REPEATED

START

D1h

11010001

SLAVE

ACK

DATA

VALUE

MASTER

NACK

STOP

C) MULTIBYTE WRITE

-WRITE DATE REGISTER

TO "02" AND MONTH

REGISTER TO "11"

D) MULTIBYTE READ

-READ ALARM 2 HOURS

AND DATE VALUES

D0h

04h

02h

START

11010000

SLAVE

ACK

00000100

SLAVE

ACK

00000010

SLAVE

ACK

11h

00010001

SLAVE

ACK

STOP

D0h

0Ch

START

11010000

SLAVE

ACK

00001100

SLAVE

ACK

REPEATED

START

D1h

11010001

SLAVE

ACK

DATA

VALUE

MASTER

ACK

DATA

VALUE

MASTER

NACK

STOP

Figure 9. I2C Transactions

reads data with ACK or NACK as applicable, and

generates a STOP condition. See Figure 6 for a read

example using the repeated START condition to

specify the starting memory location.

Reading Multiple Bytes from a Slave: The read

operation can be used to read multiple bytes with a

single transfer. When reading bytes from the slave,

the master simply ACKs the data byte if it desires to

read another byte before terminating the transaction.

After the master reads the last byte it must NACK to

indicate the end of the transfer and then it generates

a STOP condition.

Applications Information

Power-Supply Decoupling

To achieve the best results when using the DS3231M,

decouple the VCC and/or VBAT power supplies with

0.1FF and/or 1.0FF capacitors. Use a high-quality,

ceramic, surface-mount capacitor if possible. Surface-

mount components minimize lead inductance, which

improves performance, and ceramic capacitors tend to

have adequate high-frequency response for decoupling

applications.

If communications during battery operation are not

required, the VBAT decoupling capacitor can be omitted.

Using Open-Drain Outputs

The 32KHZ and INT/SQW outputs are open drain and

therefore require external pullup resistors to realize logic-

high output levels. Pullup resistor values between 1kI

and 10MI are typical.

The RST output is also open drain, but is provided with

an internal 50kI pullup resistor (RPU) to VCC. External

pullup resistors should not be added.

SDA and SCL Pullup Resistors

SDA is an open-drain output and requires an external

pullup resistor to realize a logic-high level.

Because the device does not use clock cycle stretching,

a master using either an open-drain output with a pullup

resistor or CMOS output driver (push-pull) could be used

for SCL.

Battery Charge Protection

The device contains Maxim’s redundant battery-charge

protection circuit to prevent any charging of the external

battery.

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