DS3232MZ View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
'DS3232MZ' PDF : 23 Pages View PDF
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Test Register (13h)
NAME:
POR*:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
SWRST
0
0
0
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
BIT 1
0
0
BIT 0
0
0
This register is used for factory test. Bits 6:0 are locked and always read as zeros. Writing to bit locations 6:0 has no affect on the
device. If the SWRST bit is set to Logic 1, the device immediately resets all internal logic and registers (except the SRAM) to their
factory-default POR state.
The device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that SWRST
instruction; a NACK occurs due to the resetting action (see Figure 8). The I/O master should terminate the I/O string with a nor-
mal STOP instruction (on the 28th SCL clock). The SWRST bit is automatically cleared to logic 0.
SLAVE ACKs
NACK DURING SWRST
SDA
1 1 01 0 0 0 0
0 00 100 11
10000000
SLAVE ADDRESS
R/W
REGISTER ADDRESS
DATA
SCL
Figure 8. Software Reset I/O Execution
NAME:
POR*:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
D7
D6
D5
D4
D3
D2
X
X
X
X
X
X
*POR is defined as the first application of power to the device, either VBAT or VCC.
SRAM (14h–FFh)
BIT 1
D1
X
BIT 0
D0
X
  19
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