DSA400 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'DSA400' PDF : 20 Pages View PDF
3.0 OPERATIONAL DESCRIPTION
The DSA400 is a clock generator. Unlike older clock
generators in the industry, it does not require an
external crystal to operate; it relies on the integrated
MEMS resonator that interfaces with internal PLLs.
This technology enhances performance and reliability
by allowing tighter frequency stability over a far wider
temperature range. In addition, the higher resistance to
shock and vibration decreases the aging rate to allow
for much improved product life in the system.
3.1 Inputs
There are four input signals in the device. Each has an
internal (40 kΩ) pull-up to default the selection to a high
(1). Inputs can be controlled through hardware
strapping method with a resistor to ground to assert the
input low (0). Inputs may also be controlled by other
components’ GPIOs
In case more than one frequency set is desired, FSB1
and FSB2 are used to independently select one of two
sets per bank. FSB1 selects the pre-configured set on
Bank1 (CLK0 and CLK3) and FSB2 selects the
pre-configured set on Bank2 (CLK1 and CLK2), as
shown in Table 0-1 in the Product Identification System
section.
If there is a requirement to disable outputs, the inputs
OE1 and OE2 are used in conjunction to disable the
banks of outputs. Outputs are disabled in tri-state (Hi-Z)
mode. See Table 3-1 for more information.
TABLE 3-1: OUTPUT ENABLE
SELECTION TABLE
OE1 OE2
Bank 1
(CLK0 & CLK3)
Bank 2
(CLK1 & CLK2)
00
01
10
11
Hi-Z
Hi-Z
Running
Running
Hi-Z
Running
Hi-Z
Running
3.2 Outputs
The four outputs are grouped into two banks. Each
bank is supplied by an independent VDD to allow for
optimized noise isolation between the two banks. Each
bank provides two synchronous outputs generated by
a common PLL:
• Bank1 is composed of outputs CLK0 and CLK3.
• Bank2 is composed of outputs CLK1 and CLK2.
Each output may be pre-configured independently to
be one of the following formats: LVCMOS, LVDS,
LVPECL or HCSL. In case the output is configured to
be single-ended LVCMOS, the frequency is generated
on the true output (CLKx+) and the complement output
(CLKx–) is shut off in a low state. Frequencies can be
DSA400
chosen from 2.3 MHz to 460 MHz for differential
outputs and from 2.3 MHz to 170 MHz on LVCMOS
outputs.
3.3 Power
VDD1 and VDD2 supply the power to banks 1 and 2
respectively. Each VDD may have a different supply
voltage from the other as long as it is within the 2.25V
to 3.6V range. Each VDD pin should have a 0.1 μF
capacitor to filter high-frequency noise. VSS is common
to the entire device.
2020 Microchip Technology Inc.
DS20006356A-page 5
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