DSA400 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'DSA400' PDF : 20 Pages View PDF
4.2 LVDS
DSA400
100 Ω
100 Ω
Load (receiver IC)
FIGURE 4-2:
Typical LVDS Termination Scheme.
If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and
placed as close as possible to the receiver.
TABLE 4-2: LVDS OUTPUTS
Parameter Symbol
Min.
Typ.
Max.
Units
Condition
Output Offset
Voltage
VOS
1.125
—
1.46
V R = 100Ω Differential
Delta Offset
Voltage
∆VOS
—
—
100
mV —
Peak-to-Peak
Output Swing
VPP
—
350
—
mV Single-Ended
Output
tR
Transition Time
(Note 1)
tF
—
200
—
—
200
—
Rise Time, 20% to 80%, RL= 50Ω,
ps CL= 2 pF
Fall Time, 20% to 80%, RL= 50Ω,
CL= 2 pF
Frequency
f0
2.3
—
460
MHz Single Frequency
Output Duty
Cycle
SYM
48
—
52
% Differential
IO Supply
Current (Note 2)
IDDIO
—
9
12
mA Per Output at 125 MHz
Period Jitter
JPER
—
2.5
—
psRMS
Integrated
Phase Noise
JPH
—
0.28
—
—
0.4
—
psRMS
—
1.7
2.0
Note 1: See the Output Waveform section for more information.
—
200 kHz to 20 MHz @ 156.25 MHz
100 kHz to 20 MHz @ 156.25 MHz
12 kHz to 20 MHz @156.25 MHz
2: The addition of IDDCORE and IDDIO provides the total current consumption of the device.
2020 Microchip Technology Inc.
DS20006356A-page 7
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