DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
Instruction Sequences
Reading Flash Memory
An instruction sequence consists of a sequence of Under typical conditions, the DSP may read the
specific write or read operations. Each byte written Flash memory using read operations just as it
to the device is received and sequentially decoded would a ROM or RAM device. Alternately, the DSP
and not executed as a standard write operation to may use read operations to obtain status informa-
the memory array. The instruction sequence is ex- tion about a Program or Erase cycle that is cur-
ecuted when the correct number of bytes are prop- rently in progress. Lastly, the DSP may use
erly received and the time between two instruction sequences to read special data from
consecutive bytes is shorter than the time-out pe- these memory blocks. The following sections de-
riod. Some instruction sequences are structured to scribe these read instruction sequences.
include read operations after the initial write oper-
ations.
Read Memory Contents. Flash memory is
placed in the Read Array mode after Power-up,
The instruction sequence must be followed exact- chip reset, or a Reset Flash memory instruction
ly. Any invalid combination of instruction bytes or sequence (see Table 5). The DSP can read the
time-out between two consecutive bytes while ad- memory contents of the Flash memory by using
dressing Flash memory resets the device logic into read operations any time the read operation is not
Read Array mode (Flash memory is read like a part of an instruction sequence.
ROM device). The device supports the instruction Read Flash Identifier. The Flash memory identi-
sequences summarized in Table 5:
Flash memory:
t(s) ■ Erase memory by chip or sector
■ Suspend or resume sector erase
uc ■ Program a Byte
rod ■ Reset to Read Array mode
■ Read primary Flash Identifier value
te P ■ Read Sector Protection Status
le These instruction sequences are detailed in Table
5. For efficient decoding of the instruction se-
so quences, the first two bytes of an instruction se-
b quence are the coded cycles and are followed by
an instruction byte or confirmation byte. The coded
O cycles consist of writing the data AAh to address
- XX555h during the first cycle and data 55h to ad-
t(s) dress XXAAAh during the second cycle. Address
signals A17-A12 are Don’t Care during the instruc-
c tion sequence Write cycles. However, the appro-
u priate internal Sector Select (FS0-FS7) must be
rod selected internally (active, which is logic 1).
fier is read with an instruction sequence composed
of 4 operations: 3 specific write operations and a
read operation (see Table 5). During the read op-
eration, address bits A6, A1, and A0 must be
0,0,1, respectively, and the appropriate internal
Sector Select (FS0-FS7) must be active. The iden-
tifier 0xE3.
Read Memory Sector Protection Status. The
Flash memory Sector Protection Status is read
with an instruction sequence composed of 4 oper-
ations: 3 specific write operations and a read oper-
ation (see Table 5). During the read operation,
address bits A6, A1, and A0 must be 0,1,0, re-
spectively, while internal Sector Select (FS0-FS7)
designates the Flash memory sector whose pro-
tection has to be verified. The read operation pro-
duces 01h if the Flash memory sector is protected,
or 00h if the sector is not protected.
The sector protection status can also be read by
the DSP accessing the Flash memory Protection
register in csiop space. See the section entitled
“Flash Memory Sector Protect” for register defini-
tions.
P Table 6. Status Bit Definition
te Functional Block
FS0-FS7
DQ7 DQ6 DQ5
sole Flash Memory
Active (the desired
Data Toggle Error
segment is selected) Polling Flag Flag
ObNote: 1. X = Not guaranteed value, can be read either 1 or 0.
DQ4
X
DQ3
Erase
Time-
out
DQ2
X
DQ1
X
DQ0
X
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
Reading the Erase/Program Status Bits. The
device provides several status bits to be used by
the DSP to confirm the completion of an Erase or
Program cycle of Flash memory. These status bits
minimize the time that the DSP spends performing
these tasks and are defined in Table 6. The status
bits can be read as many times as needed.
For Flash memory, the DSP can perform a read
operation to obtain these status bits while an
Erase or Program instruction sequence is being
executed by the embedded algorithm. See the
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