DSP56300FM View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

DSP56300FM

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

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External Clock Operation

Table 3-4 Internal Clocks (continued)

Characteristics

Expression1, 2

Symbol

Min

Typ

Max

Internal clock low period

• With PLL disabled

• With PLL enabled and MF ≤ 4

TL

—

ETC

—

0.49 × ETC ×

—

0.51 × ETC ×

PDF × DF/MF

PDF × DF/MF

• With PLL enabled and MF > 4

0.47 × ETC ×

—

0.53 × ETC ×

PDF × DF/MF

PDF × DF/MF

Internal clock cycle time with PLL enabled

TC

—

ETC × PDF ×

—

DF/MF

Internal clock cycle time with PLL disabled

TC

—

2 × ETC

—

Instruction cycle time

ICYC

—

TC

—

1 DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

3.7 External Clock Operation

The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL

(See Figure 3-1).

EXTAL

VILC

ETH

2

ETL

3

4

ETC

Midpoint

VIHC

Note: The midpoint is 0.5 (VIHC + VILC).

Figure 3-1 External Clock Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-5

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