DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses1 (continued)
No.
Characteristics
Symbol
Expression2
Min Max Unit
101 Address and AA valid to WR assertion
tAS
0.25 × TC − 2.0
0.5
—
ns
[WS = 1]
0.75 × TC − 2.0
[2 ≤ WS ≤ 3]
5.5
—
ns
1.25 × TC − 2.0
[WS ≥ 4]
10.5 —
ns
102 WR assertion pulse width
tWP
1.5 × TC − 4.0
11.0 —
ns
[WS = 1]
All frequencies:
WS × TC − 4.0
[2 ≤ WS ≤ 3]
16.0 —
ns
(WS − 0.5) × TC − 4.0
31.0
—
ns
[WS ≥ 4]
103 WR deassertion to address not valid
tWR
0.25 × TC − 2.0
0.5
—
ns
[1 ≤ WS ≤ 3]
1.25 × TC − 2.0
[4 ≤ WS ≤ 7]
10.5 —
ns
2.25 × TC − 2.0
[WS ≥ 8]
20.5 —
ns
All frequencies:
1.25 × TC − 4.0
[4 ≤ WS ≤ 7]
8.5
—
ns
2.25 × TC − 4.0
[WS ≥ 8]
18.5 —
ns
104 Address and AA valid to input data valid
tAA, tAC
(WS + 0.75) × TC − 7.0
—
10.5
ns
[WS ≥ 1]
105 RD assertion to input data valid
tOE
(WS + 0.25) × TC − 7.0
—
5.5
ns
[WS ≥ 1]
106 RD deassertion to data not valid (data hold time)
107 Address valid to WR deassertion3
tOHZ
tAW
0.0
—
ns
(WS + 0.75) × TC − 4.0 13.5
—
ns
[WS ≥ 1]
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-13
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