DSPIC33FJ16GP304 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'DSPIC33FJ16GP304' PDF : 284 Pages View PDF
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
3.3 Special MCU Features
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
features a 17-bit by 17-bit single-cycle multiplier that is
shared by both the MCU ALU and DSP engine. The mul-
tiplier can perform signed, unsigned and mixed-sign mul-
tiplication. Using a 17-bit by 17-bit multiplier for 16-bit by
16-bit multiplication not only allows you to perform
mixed-sign multiplication, it also achieves accurate results
for special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
supports 16/16 and 32/16 divide operations, both frac-
tional and integer. All divide instructions are iterative oper-
ations. They must be executed within a REPEAT loop,
resulting in a total execution time of 19 instruction cycles.
The divide operation can be interrupted during any of
those 19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit left
or right shift in a single cycle. The barrel shifter can be
used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
Interrupt
Controller
X Data Bus
8
16
16
16
16
Data Latch Data Latch
23
PCU PCH PCL
23
Program Counter
X RAM
Y RAM
16
Stack
Control
Logic
Loop
Control
Logic
Address
Latch
Address
Latch
23
16
16
Address Latch
Address Generator Units
Program Memory
Data Latch
24
Instruction
Decode and
Control
ROM Latch
EA MUX
16 16
Instruction Reg
Control Signals
to Various Blocks
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
To Peripheral Modules
DS70290G-page 20
© 2011 Microchip Technology Inc.
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