DZPD6710VCB View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'DZPD6710VCB' PDF : 138 Pages View PDF
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.6
Card I/O Map 0–1 Offset Address Low
Register Name: Card I/O Map 0–1 Offset Address Low
Index: 36h, 38h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Register Per: socket
Register Compatibility Type: ext.
Bit 1
Bit 0
Offset Address 7:1
01
1. This bit must be programmed to ‘0’.
RW:0000000
RW:0
There are two separate Card I/O Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index Card I/O Map Offset Address Low
36h Card I/O Map 0 Offset Address Low
38h Card I/O Map 1 Offset Address Low
Bits 7:1 — Offset Address 7:1
This register contains the least-significant byte of the quantity that will be added to the host I/O
address; this will determine the PC Card I/O map location where the I/O access will occur.
The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register (see
“Card I/O Map 0–1 Offset Address High” on page 62).
8.7
Card I/O Map 0–1 Offset Address High
Register Name: Card I/O Map 0–1 Offset Address High
Index: 37h, 39h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Register Per: socket
Register Compatibility Type: ext.
Bit 1
Bit 0
Offset Address 15:8
RW:00000000
There are two separate Card I/O Map Offset Address High registers, each with identical fields.
These registers are located at the following indexes:
Index Card I/O Map Offset Address High
37h Card I/O Map 0 Offset Address High
39h Card I/O Map 1 Offset Address High
62
Datasheet
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