DZPD6710VCB View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'DZPD6710VCB' PDF : 138 Pages View PDF
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bits 7:0 — Offset Address 19:12
This register contains the least-significant byte of the quantity that will be added to the host
memory address, which will determine where the memory access will occur in the PC Card
memory map.
The most-significant six bits are located in the Card Memory Map 0–4 Offset Address High
register (see “Card Memory Map 0–4 Offset Address High” on page 68).
9.6
Card Memory Map 0–4 Offset Address High
Register Name: Card Memory Map 0–4 Offset Address High
Index: 15h, 1Dh, 25h, 2Dh, 35h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Register Per: socket
Register Compatibility Type: 365
Bit 1
Bit 0
Write Protect REG Setting
Offset Address 25:20
RW:0
RW:0
RW:000000
There are five separate Card Memory Map Offset Address High registers, each with identical
fields. These registers are located at the following indexes:
Index
15h
1Dh
25h
2Dh
35h
Card Memory Map Offset Address High
Card Memory Map 0 Offset Address High
Card Memory Map 1 Offset Address High
Card Memory Map 2 Offset Address High
Card Memory Map 3 Offset Address High
Card Memory Map 4 Offset Address High
Bits 5:0 — Offset Address 25:20
This field contains the most-significant six bits of the Offset Address. See the description of the
Offset Address field associated with bits 7:0 of the Card Memory Map 0–4 Offset Address Low
register (see “Card Memory Map 0–4 Offset Address Low” on page 67).
Bit 6 — REG Setting
0
-REG (see Table 2 on page 20) is not active for accesses made through this window.
1
-REG is active for accesses made through this window.
This bit determines whether -REG ( Table 2) will be active for accesses made through this window.
Card Information Structure (CIS) memory is accessed by setting this bit to ‘1’.
68
Datasheet
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