E-STE10/100A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'E-STE10/100A' PDF : 82 Pages View PDF
Registers and descriptors description
STE10/100A
Table 8.
Bit #
Control/status register description (continued)
Name
Description
CSR7 (offset = 38h), IER - Interrupt enable register
31~17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
--- Reserved
Normal interrupt enable.
NIE 1: enables all the normal interrupt bits (see bit 16
of CSR5).
Abnormal interrupt enable.
AIE 1: enables all the abnormal interrupt bits (see bit
15 of CSR5).
--- Reserved
FBEIE
Fatal bus error interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the fatal bus error interrupt.
--- Reserved
GPTIE
General purpose timer interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the general purpose timer
expired interrupt.
--- Reserved
RWTIE
Receive watchdog time-out interrupt enable
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the receive watchdog time-out
interrupt.
RSIE
Receive stopped interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the receive stopped interrupt.
RUIE
Receive descriptor unavailable interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the receive descriptor
unavailable interrupt.
RCIE
Receive completed interrupt enable.
1: this bit in conjunction with NIE (bit 16 of
CSR7) will enable the receive completed
interrupt.
TUIE
Transmit under-flow interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the transmit under-flow
interrupt.
--- Reserved
TJTTIE
Transmit jabber timer time-out interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the transmit jabber timer time-
out interrupt.
Default
0
0
0
0
0
0
0
0
0
0
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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