E-STE10/100A View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

E-STE10/100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STMicroelectronics 

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Registers and descriptors description

STE10/100A

Table 8.

Bit #

Control/status register description (continued)

Name

Description

Default

0024h

0028h

002ch

0030h

0034h

0038h

CRC16 of pattern 2

Reserved

Wake-up pattern 3 mask bits 31:0

Wake-up pattern 3 mask bits 63:32

Wake-up pattern 3 mask bits 95:64

Wake-up pattern 3 mask bits 127:96

CRC16 of pattern 3

Reserved

003ch

0040h

0044h

0048h

004ch

0050h

0054h

0058h

005ch

0060h

Wake-up pattern 4 mask bits 31:0

Wake-up pattern 4 mask bits 63:32

Wake-up pattern 4 mask bits 95:64

Wake-up pattern 4 mask bits 127:96

CRC16 of pattern 4

Reserved

Wake-up pattern 5 mask bits 31:0

Wake-up pattern 5 mask bits 63:32

Wake-up pattern 5 mask bits 95:64

Wake-up pattern 5 mask bits 127:96

CRC16 of pattern 5

Reserved

RW type

Wake-up

pattern 2

offset

Wake-up

pattern 3

offset

Wake-up

pattern 4

offset

Wake-up

pattern 5

offset

Offset value is from 0-255 (8-bit width). To load the whole wake-up frame filtering information, consecutive 25

long words write operation to CSR14 should be done.

CSR15 (offset = 78h), WTMR - Watchdog timer

31~6

5

4

---

RWR

RWD

Reserved

Receive watchdog release. The time (in bit-

times) from sensing dropped carrier to releasing

watchdog timer.

0: 24 bit-times

1: 48 bit-times

Receive watchdog disable

0: If the received packet‘s length exceeds 2560

bytes, the watchdog timer will expire.

1: disable the receive watchdog.

3

--- Reserved

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