EM78862B
8-Bit RISC Type Microprocessor
6.1.5 R4 (Register Bank Select Register)
Bit 7
RBK1
Bit 6
RBK0
Bit 5
FSR5
Bit 4
FSR4
Bit 3
FSR3
Bit 2
FSR2
Bit 1
FSR1
Bit 0
FSR0
Bits 0 ~ 5: Used to select up to 32 registers in indirect address mode of each bank
Bits 6 ~ 7: Determine which bank is activated among the 4 banks
Refer to Fig. 4; Data Memory Configuration (previous page) for configuration of the data
memory
6.1.6 R5 (Program Page Select Register)
Bit 7
R57
Bit 6
R56
Bit 5
R55
Bit 4
R54
Bit 3
PS3
Bit 2
PS2
Bit 1
PS1
Bit 0
PS0
Bit 0 ~ 3: (PS0 ~ PS3) Page select bits as shown below:
PS3 PS2 PS1 PS0 Program Memory Page (Address)
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
::
::
1
1
1
0
Page 14
1
1
1
1
Page 15
You can use PAGE instruction to change and maintain program page. Otherwise,
use far jump (FJMP) or far call (FCALL) MACRO instructions to program user's
code. ÉLAN’s complier supports program page maintenance and can change
your program by inserting instructions within its program.
Bit 4 ~ 7: 4-bit I/O registers of Port 5
6.1.7 R6 (Port 6)
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 0:
(R60) Port 6, single bit (Bit 0) I/O register
Bit 1 ~ 7: Unused
Bit 2
-
Bit 1
-
Bit 0
R60
6.1.8 R7 (Port 7)
Bit 7
R77
Bit 6
R76
Bit 5
R75
Bit 4
R74
Bit 0 ~ 7: Port 7 8-bit I/O registers
Bit 3
R73
Bit 2
R72
Bit 1
R71
Bit 0
R70
This specification is subject to change without further notice.
Mar.01.2005 (V1.1) 7 of 36