EM78862B
8-Bit RISC Type Microprocessor
6.2.5 IOC7 (Port 7 I/O Control Register)
Bit 7
IOC77
Bit 6
IOC76
Bit 5
IOC75
Bit 4
IOC74
Bit 3
IOC73
Bit 2
IOC72
Bit 0 ~ 7: (IOC70 ~ IOC77) Port 7 I/O direction control register
0: Set the relative I/O pins as output
1: Set the relative I/O pin into high impedance
Bit 1
IOC71
Bit 0
IOC70
6.2.6 IOC8 (Port 8 I/O Control Register)
Bit 7
IOC87
Bit 6
IOC86
Bit 5
IOC85
Bit 4
IOC84
Bit 3
IOC83
Bit 2
IOC82
Bit 0 ~ 7: (IOC80 ~ IOC87) Port 8 I/O direction control register
0: Set the relative I/O pins as output
1: Set the relative I/O pin into high impedance
Bit 1
IOC81
Bit 0
IOC80
NOTE
Refer to Section 6.2.8, IOCA (Bit6/7) Register below on how to switch Port 8 to
normal I/O port.
6.2.7 IOC9 (Port 9 I/O Control Register)
Bit 7
IOC97
Bit 6
IOC96
Bit 5
IOC95
Bit 4
IOC94
Bit 3
IOC93
Bit 2
IOC92
Bit 0 ~7: (IOC90 ~ IOC97) Port 9 I/O direction control register
0: Set the relative I/O pins as output
1: Set the relative I/O pin into high impedance
Bit 1
IOC91
Bit 0
IOC90
NOTE
Refer to Section 6.2.12, IOCE (Bit6/7) Register on how to switch Port 9 to normal I/O port.
6.2.8 IOCA (2K RAM Bank, Port 8 I/O, Page Control Register, R/W,
Default "00000000")
Bit 7
P8SH
Bit 6
P8SL
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
0 RAMBK2 RAMBK1 RAMBK0
Bit 0: Unused. Clear to ‘0’
Bit 1 ~ 3: (RAMBK0 ~ RAMBK2) Select 640 bytes RAM bank.
Bit 0
0
RAMBK_2
0
0
0
0
1
1
1
1
RAMBK_1
0
0
1
1
0
0
1
1
RAMBK_0
0
1
0
1
0
1
0
1
Note (Total Size)
RAM BANK0 (256 Bytes)
RAM BANK1 (256 Bytes)
RAM BANK2 (256 Bytes)
RAM BANK3 (256 Bytes)
RAM BANK4 (256 Bytes)
RAM BANK5 (256 Bytes)
RAM BANK6 (256 Bytes)
RAM BANK7 (256 Bytes)
This specification is subject to change without further notice.
Mar.01.2005 (V1.1)13 of 36