EMC6D102-CZC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
EMC6D102-CZC
SMSC -> Microchip
'EMC6D102-CZC' PDF : 86 Pages View PDF
7.2.27
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Register 7Ch: Special Function Register
Datasheet
Register
Address
7Ch
Read/
Write
R/W
Register Name
Special Function
Bit 7
(MSb)
AVG2
Bit 6
AVG1
Bit 5
AVG0
Bit 4
SMSC
Bit 3
SMSC
Bit 2
Bit 1
Bit 0 Default
(LSb) Value
INTEN MONMD LPMD
40h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
This register contains the following bits:
Bit[0] Low-Power Mode Select
0= Sleep Mode (default)
1= Shutdown Mode
Bit[1] Monitoring Mode Select
0= Continuous Monitor Mode (default)
1= Cycle Monitor Mode
Bit[2] INT# Enable
0=Disables INT# pin output function (default)
1=Enables INT# pin output function
Bit[3] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted
results.
Bit [4] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause
unwanted results.
Bits [7:5] AVG[2:0]
The AVG[2:0] bits determine the amount of averaging for each of the six measurements that are
performed by the hardware monitor before the reading registers are updated (TABLE 22). The
AVG[2:0] bits are priority encoded where the most significant bit has highest priority. For example,
when the AVG2 bit is asserted, 32 averages will be performed for each measurement before the
reading registers are updated regardless of the state of the AVG[1:0] bits.
Table 7.17 AVG[2:0] Bit Decoder
SFTR[7:5]
AVERAGES PER READING
ALL VOLTAGE READINGS
AVG2 AVG1 AVG0 REM DIODE 1 REM DIODE 2 INTERNAL DIODE (+2.5V, +5V, +12V, VCCP, AND VCC)
0
0
0
128
128
8
8
0
0
1
16
16
1
1
0
1
X
16
16
16
16
1
X
X
32
32
32
32
Note: The default for the AVG[2:0] bits is ‘010’b.
Revision 0.4 (04-05-05)
68
DATASHEET
SMSC EMC6D102
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