EP7212-CV-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
EP7212-CV-A
Cirrus Logic
'EP7212-CV-A' PDF : 136 Pages View PDF
EP7212
EXPCLK
nCS[5:0]
nMOE
A[27:4]
0
WORD
tEXBST
4
tEXBST
8
D[31:0]
Bus held
EXPRDY
t1
tEXRD
t3 t4
Data in
t3 t4
Data in
t3 t4
Data in
t5
t6
Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States
NOTES:
1) tEXBST = 35 ns at 36.864 MHz
35 ns at 18.432 MHz
55 ns at 13.0 MHz
(Value for 36.864 MHz assumes 1 wait state.)
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 nsec at 36 MHz, 54 nsec at 18.432 MHz and 77 ns at 13 MHz), by either driving
EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock
period where EXPRDY is sampled again. EXPCLK need not be referenced when driving
EXPRDY, but is shown for clarity.
2) Consecutive reads with sequential access enabled are identical except that the sequential
access wait state field is used to determine the number of wait states, and no idle cycles are
inserted between successive non-sequential ROM/expansion cycles. This improves perfor-
mance so the SQAEN bit should always be set where possible.
DS474PP1
101
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