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EP7312-EB View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
'EP7312-EB' PDF : 64 Pages View PDF
SDRAM Load Mode Register Cycle
SDCLK
SDCS
SDRAS
SDCAS
ADDR
DATA
SDQM
SDMWE
tCSa
tRAa
tCAa
tADv
tMWa
EP7312
High-Performance, Low-Power System on Chip
tCSd
tRAd
tCAd
tADx
tMWd
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
DS508PP5
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
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