EVAL-AD1837EB View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD1837EB

2 ADC, 8 DAC, 96 kHz, 24-Bit Σ-Δ Codec

Analog Devices

'EVAL-AD1837EB' PDF : 24 Pages View PDF

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CLATCH
tCLS
tCCP
CCLK
CIN
D15
D14
COUT
tCOE
tCCH tCCL
tCDS tCDH
D9
D8
D9
D8
tCOD
Figure 3. Format of SPI Timing
AD1837
tCLH
tCOTS
D0
D0
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
I2S MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LSB
MSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/ fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 ؋ fS.
3. BCLK FREQUENCY IS NORMALLY 64 ؋ LRCLK BUT MAY BE OPERATED IN BURST MODE.
LSB
Figure 4. Stereo Serial Modes
REV. B
–13–

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