LRCLK
BCLK
ADC DATA
256 BCLKs
32 BCLKs
SLOT 1
LEFT
SLOT 2
SLOT 3
SLOT 4
SLOT 5
RIGHT
SLOT 6
SLOT 7
SLOT 8
AD1837
MSB MSB – 1 MSB – 2
Figure 7. ADC Packed Mode 256
LRCLK
BCLK
DAC DATA
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
MSB MSB – 1 MSB – 2
Figure 8. DAC Packed Mode 256
ABCLK
ALRCLK
ASDATA
tABH
tABP
tABL
tALS
tALH
tADS
MSB
tADH
MSB – 1
tABDD
Figure 9. ADC Packed Mode Timing
DBCLK
DLRCLK
DSDATA
tDBH
tDBP
tDBL
tDLS
tDLH
tDDS
MSB
tDDH
MSB – 1
Figure 10. DAC Packed Mode Timing
REV. B
–15–