EVAL-AD1940EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD1940EB' PDF : 32 Pages View PDF
AD1940/AD1941
The total number of bytes for a single location write command
can vary from four bytes (for a control register write), to eight
bytes (for a program RAM write). Burst mode may be used to
fill contiguous register or RAM locations. A burst mode write is
done by writing the address and data of the first RAM/register
location to be written. Rather than ending the control port
transaction (by bringing the CLATCH signal high in the
AD1940/AD1941, after the data word, as would be done in a
single address write, the next data word can be written
immediately without first writing its specific address). The
AD1940/AD1941 control ports autoincrement the address of
each write, even across the boundaries of the different RAMs
and registers.
Table 26. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
chip_adr [6:0], W/R
0000, param_adr [11:8]
param_adr [7:0]
Byte 3
0000, param [27:24]
Bytes 4–6
param [23:0]
Table 27. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Byte 3
chip_adr [6:0], W/R 0000, param_adr [11:8] param_adr [7:0] 0000, param [27:24]
Bytes 4–6
param [23:0]
<—param_adr—>
Bytes 7-10
0000, param [27:0]
param_adr + 1
Bytes 11-141
0000, param
[27:0]
param_adr + 2
1 Burst mode data transfers can continue beyond the three words that are illustrated here in the same sequential word format. The register/RAM address auto-
increments until the data transfer reaches the IC's last address.
Table 28. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
chip_adr [6:0], W/R
0000, prog_adr [11:8]
prog_adr [7:0]
Bytes 3–7
prog [39:0]
Table 29. Program RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Bytes 3-7
chip_adr [6:0], W/R 0000, prog_adr [11:8] prog_adr [7:0] prog [39:0]
<—prog_adr—>
Bytes 8-12
prog [39:0]
prog_adr +1
Bytes 13-171
prog [39:0]
prog_adr +2
1 Burst mode data transfers can continue beyond the three words that are illustrated here in the same sequential word format. The register/RAM address auto-
increments until the data transfer reaches the IC's last address.
Table 30. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1)
Byte 0
Byte1
Byte 2
chip_adr [6:0], W/R
0000, reg_adr [11:8]
reg_adr [7:0]
Byte 3
data [15:8]
Byte 4
data [7:0]
Table 31. Control Register Read/Write Format (RAM Configuration, Serial Input)
Byte 0
Byte1
Byte 2
chip_adr [6:0], W/R
0000, reg_adr [11:8]
reg_adr [7:0]
Byte 3
data [7:0]
Rev. A | Page 26 of 36
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