AD5122/AD5142
Data Sheet
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8 DB7
DB0 (LSB)
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
SYNC
SDI
CONTROL BITS
t4
t8
t2
t3
ADDRESS BITS
DATA BITS
Figure 2. Input Shift Register Contents
t1
C3
C2
C1
C0
D7
D6
D5
D2
t7
t5
t6
D1
D0
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
t9
t10
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 3. SPI Serial Interface Timing Diagram, Clock Polarity (CPOL) = 0, Clock Phase (CPHA) = 1
t4
t2
t1
t7
SCLK
t8
t3
SYNC
t5
t6
SDI
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
t9
D2*
t10
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 4. SPI Serial Interface Timing Diagram, Clock Polarity (CPOL) = 1, Clock Phase (CPHA) = 0
SCLK
SYNC
RESET
t1
Figure 5. Control Pins Timing Diagram
Rev. C | Page 10 of 32