EVAL-AD5142DBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5142DBZ
Analog Devices
'EVAL-AD5142DBZ' PDF : 32 Pages View PDF
Data Sheet
AD5122/AD5142
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface1
Parameter2 Test Conditions/Comments
t1
VLOGIC > 1.8 V
VLOGIC = 1.8 V
t2
VLOGIC > 1.8 V
VLOGIC = 1.8 V
t3
VLOGIC > 1.8 V
VLOGIC = 1.8 V
t4
t5
t6
t7
t83
t94
t10
Min Typ Max Unit Description
20
ns
SCLK cycle time
30
ns
10
ns
SCLK high time
15
ns
10
ns
SCLK low time
15
ns
10
ns
SYNC to SCLK falling edge setup time
5
ns
Data setup time
5
ns
Data hold time
10
ns
SYNC rising edge to next SCLK fall ignored
20
ns
Minimum SYNC high time
50
ns
SCLK rising edge to SDO valid
500 ns
SYNC rising edge to SDO pin disable
1 Refer to the AN-1248 for additional information about the serial peripheral interface.
2 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3
Refer
to
t
EEPROM_PROGRAM
and
t
EEPROM_READBACK
for
memory
commands
operations
(see
Table
5).
4 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. Control Pins
Parameter
Min Typ Max Unit Description
t1
t1
EEPROM_PROGRAM
tEEPROM_READBACK
t2
POWER_UP
tRESET
0.1
10
µs
RESET low time
15
50
ms
Memory program time (not shown in Figure 5)
7
30
µs
Memory readback time (not shown in Figure 5)
75
µs
Start-up time (not shown in Figure 5)
30
µs
Reset EEPROM restore time (not shown in Figure 5)
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
Rev. C | Page 9 of 32
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