AD5372/AD5373
Parameter
POWER REQUIREMENTS
DVCC
VDD
VSS
Power Supply Sensitivity2
∆Full Scale/∆VDD
∆Full Scale/∆VSS
∆Full Scale/∆DVCC
DICC
IDD
ISS
Power-Down Mode
DICC
IDD
ISS
Power Dissipation (Unloaded)
Junction Temperature3
AD53721
B Version
AD53731
B Version
2.5/5.5
9/16.5
−16.5/−4.5
2.5/5.5
9/16.5
−16.5/−4.5
−75
−75
−75
−75
−90
−90
2
2
16
16
18
18
−16
−16
−18
−18
5
5
35
35
−35
−35
250
250
130
130
1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization; not production tested.
3 θJA represents the package thermal impedance.
Unit
V min/V max
V min/V max
V min/V max
dB typ
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
μA typ
μA typ
μA typ
mW typ
°C max
Test Conditions/Comments2
DVCC = 5.5 V, VIH = DVCC, VIL = GND
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Bit 0 in the control register is 1
VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V
TJ = TA + PTOTAL × θJA
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
B Version Unit
Test Conditions/Comments
20
μs typ
Full-scale change
30
μs max
DAC latch contents alternately loaded with all 0s and all 1s
1
V/μs typ
5
nV-s typ
10
mV max
100
dB typ
VREF0, VREF1 = 2 V p-p, 1 kHz
10
nV-s typ
0.2
nV-s typ
0.02
nV-s typ
Effect of input bus activity on DAC output under test
250
nV/√Hz typ VREF0 = VREF1 = 0 V
1 Guaranteed by design and characterization; not production tested.
Rev. C | Page 5 of 28