EVAL-AD5405EB View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD5405EB

Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface

Analog Devices 

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AD5405

PARALLEL INTERFACE

Data is loaded into the AD5405 in a 12-bit parallel word format.

Control lines CS and R/W allow data to be written to or read

from the DAC register. A write event takes place when CS and

R/W are brought low, data available on the data lines fills the

shift register, and the rising edge of CS latches the data and

transfers the latched data-word to the DAC register. The DAC

latches are not transparent; therefore, a write sequence must

consist of a falling and rising edge on CS to ensure that data is

loaded into the DAC register and that its analog equivalent is

reflected on the DAC output. A read event takes place when

R/W is held high and CS is brought low. Data is loaded from the

DAC register, goes back into the input register, and is output

onto the data line, where it can be read back to the controller for

verification or diagnostic purposes. The input and DAC

registers of these devices are not transparent; therefore, a falling

and rising edge of CS is required to load each data-word.

MICROPROCESSOR INTERFACING

ADSP-21xx-to-AD5405 Interface

Figure 38 shows the AD5405 interfaced to the ADSP-21xx

series of DSPs as a memory-mapped device. A single wait state

may be necessary to interface the AD5405 to the ADSP-21xx,

depending on the clock speed of the DSP. The wait state can be

programmed via the data memory wait state control register of

the ADSP-21xx (see the ADSP-21xx family’s user manual for

details).

ADDR0 TO

ADRR13

ADDRESS BUS

ADSP-21xx1

DMS

ADDRESS

DECODER

AD54051

CS

WR

R/W

DB0 TO DB11

DATA 0 TO

DATA 23

DATA BUS

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 38. ADSP21xx-to-AD5405 Interface

8xC51-to-AD5405 Interface

Figure 39 shows the interface between the AD5405 and the

8xC51 family of DSPs. To facilitate external data memory

access, the address latch enable (ALE) mode is enabled. The low

byte of the address is latched with this output pulse during

access to the external memory. AD0 to AD7 are the multiplexed

low order addresses and data bus; they require strong internal

pull-ups when emitting 1s. During access to external memory,

A8 to A15 are the high order address bytes. Because these ports

are open drained, they also require strong internal pull-ups

when emitting 1s.

A8 TO A15

ADDRESS BUS

80511

WR

ALE

ADDRESS

DECODER

8-BIT

LATCH

AD54051

CS

R/W

DB0 TO DB11

AD0 TO AD7

DATA BUS

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 39. 8xC51-to-AD5405 Interface

ADSP-BF5xx-to-AD5405 Interface

Figure 40 shows a typical interface between the AD5405 and the

ADSP-BF5xx family of DSPs. The asynchronous memory write

cycle of the processor drives the digital inputs of the DAC. The

AMSx line is actually four memory select lines. Internal ADDR

lines are decoded into AMS3–0; these lines are then inserted as

chip selects. The rest of the interface is a standard handshaking

operation.

ADDR1 TO

ADRR19

ADDRESS BUS

ADSP-BF5xx1

AMSx

ADDRESS

DECODER

AD54051

CS

AWE

R/W

DB0 TO DB11

DATA 0 TO

DATA 23

DATA BUS

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 40. ADSP-BF5xx-to-AD5405 Interface

Rev. B | Page 18 of 24

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