EVAL-AD5687RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5687RSDZ' PDF : 28 Pages View PDF
AD5689R/AD5687R
Data Sheet
SERIAL INTERFACE
The AD5689R/AD5687R have a 3-wire serial interface
(SYNC, SCLK, and SDIN) that is compatible with SPI, QSPIâ„¢,
and MICROWIRE® interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The AD5689R/AD5687R contain an SDO pin that allows
the user to daisy-chain multiple devices together (see the
Daisy-Chain Operation section) or read back data.
Input Shift Register
The input shift register of the AD5689R/AD5687R is 24 bits
wide, and data is loaded MSB first (DB23). The first four bits
are the command bits, C3 to C0 (see Table 9), followed by
the 4-bit DAC address bits, composed of DAC B, DAC A,
and two don’t care bits that must be set to 0 (see Table 8).
Finally, the data-word completes the input shift register.
The data-word comprises 16-bit or 12-bit input code, followed
by zero don’t care bits (for the AD5689R) or four don’t care bits
(for the AD5687R), as shown in Figure 43 and Figure 44, respec-
tively). These data bits are transferred to the input shift register
on the 24 falling edges of SCLK and updated on the rising edge
of SYNC.
Commands can be executed on individual DAC channels or on
both DAC channels, depending on the address bits selected.
Table 8. Address Commands
Address (n)
DAC B 0
0
DAC A
0
0
0
1
1
0
0
0
1
0
0
1
Selected DAC Channel
DAC A
DAC B
DAC A and DAC B
Table 9. Command Definitions
Command
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
…
…
…
…
1
1
1
1
Description
No operation
Write to Input Register n (dependent on LDAC)
Update DAC Register n with contents of Input Register n
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference setup register
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
Reserved
No operation in daisy-chain mode
DB23 (MSB)
C3
C2
C1
C0
DAC
B
0
DB0 (LSB)
0
DAC
A
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 43. AD5689R Input Shift Register Content
DB23 (MSB)
C3
C2
C1
C0
DAC
B
0
0
DAC
A
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
DATA BITS
DB0 (LSB)
XXX
COMM AND BITS
ADDRESS BITS
Figure 44. AD5687R Input Shift Register Content
Rev. B | Page 20 of 28
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