AD5761R/AD5721R
2.50200
2.50175
2.50150
2.50125
2.50100
2.50075
2.50050
2.50025
2.50000
–40
–20
0
25
55
85
TEMPERATURE (°C)
105
125
Figure 43. Reference Output Voltage vs. Temperature
70
60
50
40
30
20
10
0
TEMPERATURE DRIFT (ppm/°C)
Figure 44. Reference Output TC
30000
25000
20000
15000
±10V
+10V
±5V
+5V
–2.5V TO +7.5V
±3V
+16V
+20V
10000
5000
0
–5000
–10000
–15000
–30
–20
–10
0
TVVADSSD===2–5+1°2C11VV
10
20
30
40
SOURCE/SINK CURRENT (mA)
Figure 45. Source and Sink Capability of Output Amplifier with
Positive Full Scale Loaded
Data Sheet
15000
10000
5000
0
±10V
+10V
±5V
+5V
–2.5V TO +7.5V
±3V
+16V
+20V
–5000
–10000
–15000
–20000
–30
–20
–10
0
TVVADSSD===2–5+1°2C11VV
10
20
30
SOURCE/SINK CURRENT (mA)
Figure 46. Source and Sink Capability of Output Amplifier with
Negative Full Scale Loaded
0.0010
0.0009
0.0008
0.0007
VDD = +21V
VSS = –11V
TA = 25â°C
LOAD = 2kΩ || 200pF
INTERNAL REFERENCE
IDVCC 3V
IDVCC 5V
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
0
0
1
2
3
4
5
LOGIC INPUT VOLTAGE (V)
Figure 47. Supply Current vs. Logic Input Voltage
6
4
VTVADSSD===2–5+1°2C11VV
LOAD = 2kΩ||200pF
2
0
–2
–4
SYNC
±5V, ZERO SCALE TO FULL SCALE
–6
–8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
TIME (µs)
Figure 48. Full-Scale Settling Time (Rising Voltage Step), ±5 V Range
Rev. C | Page 18 of 36