Data Sheet
6
4
2
VVTADSSD===2+5–2°1C11VV
0
LOAD = 2kΩ||200pF
–2
–4
SYNC
±5V, FULL SCALE TO ZERO SCALE
–6
–8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0
TIME (µs)
8.0 10.0 12.0 14.0
Figure 49. Full-Scale Settling Time (Falling Voltage Step), ±5 V Range
12
10
TVVASDSD===2–5+1°2C11VV
8 LOAD = 2kΩ||200pF
6
4
2
0
–2
–4
–6
–8
–10
SYNC
±10V, ZERO SCALE TO FULL SCALE
–12
–3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TIME (µs)
Figure 50. Full-Scale Settling Time (Rising Voltage Step), ±10 V Range
12
SYNC
10
±10V, FULLSCALE TO ZERO SCALE
8
6
4
2
0
–2
–4
–6
–8
–10
VTVADSSD===2–5+1°2C11VV
LOAD = 2kΩ||200pF
–12
–3.0 –1.0 1.0 3.0
5.0 7.0
TIME (µs)
9.0 11.0 13.0 15.0
Figure 51. Full-Scale Settling Time (Falling Voltage Step), ±10 V Range
AD5761R/AD5721R
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–0.01
–2
–1
0
SYNC
500-CODE STEP, ±5V SPAN
1
2
TIME (µs)
TVVASDSD===2–5+1°2C11VV
LOAD = 2kΩ||200pF
3
4
5
Figure 52. 500-Code Step Settling Time, ±5 V Range
0.20
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–0.01
–2
–1
0
SYNC
500-CODE STEP, ±10V SPAN
1
2
TIME (µs)
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
3
4
5
Figure 53. 500-Code Step Settling Time, ±10 V Range
12
0nF
10
1nF
5nF
8
7nF
10nF
6
4
2
0
–2
–4
–6
–8
–10
–12
–5
0
5
10
TIME (µs)
VVSDSD
=+21V
= –11V
TA = 25°C
LOAD = 2kΩ
15
20
Figure 54. Full-Scale Settling Time at Various Capacitive Loads, ±10 V Range
Rev. C | Page 19 of 36