EVAL-AD5764REBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5764REBZ
Analog Devices
'EVAL-AD5764REBZ' PDF : 32 Pages View PDF
AD5764R
7000
6000
TA = 25°C
REFIN = 5V
5000
4000
VDD/VSS = ±15V
VDD/VSS = ±12V
3000
2000
1000
0
–1000
–10
–5
0
5
10
SOURCE/SINK CURRENT (mA)
Figure 25. Source and Sink Capability of Output Amplifier with Positive
Full Scale Loaded
10000
TA = 25°C
9000 REFIN = 5V
8000
7000
15V SUPPLIES
6000
5000
12V SUPPLIES
4000
3000
2000
1000
0
–1000
–12
–7
–2
3
8
SOURCE/SINK CURRENT (mA)
Figure 26. Source and Sink Capability of Output Amplifier with Negative
Full Scale Loaded
VDD/VSS = ±15V
TA = 25°C
REFIN = 5V
1
1µs/DIV
CH1 3.00V
M1.00µs
CH1 –120mV
Figure 27. Full-Scale Settling Time
Preliminary Technical Data
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
–2.0–1.5–1.0–0.5 0
VDD/VSS = ±12V,
REFIN = 5V,
TA = 25°C,
0x8000 TO 0x7FFF,
500ns/DIV
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TIME (µs)
Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V
VDD/VSS = ±15V
MIDSCALE LOADED
REFIN = 0V
4
50µV/DIV
CH4 50.0µV
M1.00s
CH4 26µV
Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)
T
VDD/VSS = ±12V,
REFIN = 5V, TA = 25°C,
RAMP TIME = 100µs,
LOAD = 200pF||10kΩ
1
2
3
CH1 10.0V BW CH2 10.0V
CH3 10.0mV BW
M100µs A CH1 7.80mV
T 29.60%
Figure 30. VOUT vs. VDD/VSS on Power-Up
Rev. PrA | Page 18 of 32
Share Link: 