EVAL-AD5765EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5765EBZ' PDF : 28 Pages View PDF
Data Sheet
AD5765
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −32 LSBs to +31 LSBs in 1 LSB increments as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale
and negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement.
Table 16. Programming AD5765 Fine Gain Register
REG2 REG1 REG0 A2
A1
A0
1
0
0
DAC address
DB15:DB6
Don’t care
DB5 DB4 DB3 DB2 DB1 DB0
FG5 FG4 FG3 FG2 FG1 FG0
Table 17. AD5765 Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+31 LSBs
0
1
1
1
1
1
+30 LSBs
0
1
1
1
1
0
…
…
…
…
...
…
…
No Adjustment (Default)
0
0
0
0
0
0
…
…
…
…
…
…
…
−31 LSBs
1
0
0
0
0
1
−32 LSBs
1
0
0
0
0
0
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The AD5765 offset register is an 8-bit register and allows the user to adjust the offset of each channel
by −16 LSBs to +15.875 LSBs in increments of ⅛ LSB as shown in Table 18 and Table 19. The offset register coding is twos complement.
Table 18. Programming the AD5765 Offset Register
REG2 REG1 REG0 A2 A1 A0 DB15:DB8
1
0
1
DAC address
Don’t care
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
Table 19. AD5765 Offset Register Options
Offset Adjustment
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
+15.875 LSBs
0
1
1
1
1
1
1
1
+15.75 LSBs
0
1
1
1
1
1
1
0
…
…
…
…
…
…
…
…
…
No Adjustment (Default)
0
0
0
0
0
0
0
0
…
…
…
…
…
…
…
…
…
−15.875 LSBs
1
0
0
0
0
0
0
1
−16 LSBs
1
0
0
0
0
0
0
0
Rev. C | Page 21 of 28
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