EVAL-AD5765EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5765EBZ' PDF : 28 Pages View PDF
AD5765
POWER-ON STATUS
The AD5765 has multiple power supply and digital input pins.
It is important to consider the sequence in which the pins are
powered up to ensure that the AD5765 powers on in the
required state. The outputs power on either clamped to
AGNDx, driving 0 V, or driving negative full-scale output
(−4.096 V), depending on how the BIN/2sCOMP, CLR, and
LDAC pins are configured during power-up.
The CLR pin, if connected to DGND, causes the DAC registers
to be loaded with 0x0000 and the outputs to be updated;
consequently, the outputs are loaded with 0 V if BIN/2sCOMP
is connected to DGND or with negative full-scale (−4.096 V) if
BIN/2sCOMP is connected to DVCC, corresponding respectively
to the twos complement and binary voltages for the digital code
0x0000. During power-up, the state of the LDAC pin has an
identical effect to that of the CLR pin. If both the CLR and
Data Sheet
LDAC pins are connected to DVCC during power-up, the
outputs power on clamped to AGNDx and remain so until a
valid write is made to the device. Table 20 outlines the possible
output power-on states.
Table 20. Output Power-On States
BIN/2sCOMP CLR
LDAC
DGND
DGND
DGND
DGND
DGND
DVCC
DGND
DVCC
DGND
DGND
DVCC
DVCC
DVCC
DGND
DGND
DVCC
DGND
DVCC
DVCC
DVCC
DGND
DVCC
DVCC
DVCC
VOUT at Power-On
0V
0V
0V
Clamped to AGNDx
−4.096 V
−4.096 V
−4.096 V
Clamped to AGNDx
Rev. C | Page 24 of 28
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