EVAL-AD5932EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5932EBZ' PDF : 28 Pages View PDF
AD5932
Data Sheet
PROGRAMMING THE AD5932
The AD5932 is designed to provide automatic frequency scans
when the CTRL pin is triggered. The scan is controlled by a set
of registers, the addresses of which are given in Table 5. The
function of each register is described in more detail in the
Setting Up the Frequency Scan section.
The Control Register
The AD5932 contains a 12-bit control register that sets up the
operating modes, as shown in the following bit map.
D15 D14 D13 D12 D11 to D0
0
0
0
0
Control bits
This register controls the different functions and the various
output options from the AD5932. Table 6 describes the
individual bits of the control register.
To address the control register, D15 to D12 of the 16-bit serial
word must be set to 0.
Table 5. Register Addresses
Register Address
D15 D14 D13 D12 Mnemonic
0
0
0
0
CREG
0
0
0
1
NINCR
0 0 1 0 ∆f
0 0 1 1 ∆f
01
tINT
10
1
1
0
0
FSTART
1
1
0
1
FSTART
1110
1111
Name
Control bits
Number of increments
Lower 12 bits of
delta frequency
Higher 12 bits of
delta frequency
Increment interval
Reserved
Lower 12 bits of
start frequency
Higher 12 bits of
start frequency
Reserved
Reserved
Table 6. Description of Bits in the Control Register
Bit
Name
Function
D15 to D12 ADDR
D11
B24
D10
DAC ENABLE
D9
SINE/TRI
Register address bits.
Two write operations are required to load a complete word into the FSTART register and the Δf register.
When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first
write contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5
for the appropriate addresses. The write to the destination register occurs after both words have been loaded,
so the register never holds an intermediate value.
When B24 = 0, the 24-bit FSTART /Δf register operates as two 12-bit registers, one containing the 12 MSBs
and the other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered
independently of the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required.
To alter the 12 MSBs or the 12 LSBs, a single write is made to the appropriate register address. Refer to Table 5
for the appropriate addresses.
When DAC ENABLE = 1, the DAC is enabled.
When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when using only
the MSB of the DAC input data (available at the MSBOUT pin).
The function of this bit is to control what is available at the VOUT pin.
When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information,
resulting in a sinusoidal signal at the output.
When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC.
D8
MSBOUTEN When MSBOUTEN = 1, the MSBOUT pin is enabled.
When MSBOUTEN = 0, the MSBOUT is disabled (three-state).
D7
Reserved
This bit must be set to 1.
D6
Reserved
This bit must be set to 1.
D5
INT/EXT INCR When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin.
When INT/EXT INCR = 0, the frequency increments are triggered automatically.
D4
Reserved
This bit must be set to 1.
D3
SYNCSEL
This bit is active when D2 = 1. It is user-selectable to pulse at end of scan (EOS) or at each frequency
increment. When SYNCSEL = 1, the SYNCOUT pin outputs a high level at end of scan and returns to 0
at the start of the subsequent scan.
When SYNCSEL= 0, the SYNCOUT outputs a pulse of 4 × TCLOCK only at each frequency increment.
D2
SYNCOUTEN When SYNCOUTEN = 1, the SYNC output is available at the SYNCOUT pin.
When SYNCOUTEN = 0, the SYNCOP pin is disabled (three-state).
D1
Reserved
This bit must be set to 1.
D0
Reserved
This bit must be set to 1.
Rev. C | Page 16 of 28
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