EVAL-AD7730LEB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7730LEB' PDF : 52 Pages View PDF
AD7730/AD7730L
Data Register (RS2–RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex
The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Fig-
ure 5 shows a flowchart for reading from the registers on the AD7730. The register can be programmed to be either 16 bits or 24 bits
wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low
when the Data Register is updated. The RDY pin and RDY bit will return high once the full contents of the register (either 16 bits or
24 bits) have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit
will go high for at least 100 × tCLK IN, indicating when a read from the Data Register should not be initiated to avoid a transfer from
the Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low.
If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place
in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter-
face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7730.
Mode Register (RS2–RS0 = 0, 1, 0); Power On/Reset Status: 01B0 Hex
The Mode Register is a 16-bit register from which data can be read or to which data can be written. This register configures
the operating modes of the AD7730, the input range selection, the channel selection and the word length of the Data Register.
Table X outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are
in the Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default
status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writ-
ing to the registers on the part.
Table X. Mode Register
MR15
MD2 (0)
MR14
MD1 (0)
MR13
MD0 (0)
MR12
B/U (0)
MR11
DEN (0)
MR10
D1 (0)
MR9
D0 (0)
MR8
WL (1)
MR7
MR6
HIREF (1) ZERO (0)
MR5
RN1 (1)
MR4
MR3
MR2
RN0 (1) CLKDIS (0) BO (0)
MR1
CH1 (0)
MR0
CH0 (0)
Bit
Location
MR15–MR13
Bit
Mnemonic
MD2–MD0
Description
Mode Bits. These three bits determine the mode of operation of the AD7730 as outlined in
Table XI. The modes are independent, such that writing new mode bits to the Mode Register
will exit the part from the mode in which it is operating and place it in the new requested mode
immediately after the Mode Register write. The function of the mode bits is described in more
detail below.
MD2
0
0
0
0
1
1
1
1
Table XI. Operating Modes
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
Mode of Operation
Sync (Idle) Mode Power-On/Reset Default
Continuous Conversion Mode
Single Conversion Mode
Power-Down (Standby) Mode
Internal Zero-Scale Calibration
Internal Full-Scale Calibration
System Zero-Scale Calibration
System Full-Scale Calibration
REV. A
–15–
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