EVAL-AD7762EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7762EB' PDF : 28 Pages View PDF
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter
fMCLK
fICLK
t11, 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Limit at TMIN, TMAX
1
40
500
20
0.5 × tICLK
10
3
(0.5 × tICLK) + 16 ns
tICLK
tICLK
3
11
4 × tICLK
4 × tICLK
5
0
Unit
MHz min
MHz max
kHz min
MHz max
typ
ns min
ns min
max
min
min
ns min
ns max
min
min
ns min
ns min
Description
Applied master clock frequency
Internal modulator clock derived from MCLK
DRDY pulse width
DRDY falling edge to CS falling edge
RD/WR setup time to CS falling edge
Data access time
CS low read pulse width
CS high pulse width between reads
RD/WR hold time to CS rising edge
Bus relinquish time
CS low write pulse width
CS high period between address and data
Data setup time
Data hold time
1 tICLK = 1/fICLK.
2 When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK.
TIMING DIAGRAMS
DRDY
CS
RD/WR
D[0:15]
t1
t5
t6
t2
t3
t4
DATA MSW
t7
t8
LSW + STATUS
Figure 2. Parallel Interface Timing Diagram
CS
RD/WR
t11
D[0:15]
t9
t10
t12
REGISTER ADDRESS
Figure 3. AD7762 Register Write
REGISTER DATA
Rev. 0 | Page 5 of 28
AD7762
Share Link: 
