EVAL-AD7763EB View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD7763EB

24-Bit, 625 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers, Serial Interface

Analog Devices 

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Data Sheet

Sampling Switch SS1 and Sampling Switch SS3 are driven by ICLK,

whereas Sampling Switch SS2 and Sampling Switch SS4 are driven

by ICLK. When ICLK is high, the analog input voltage is connected

to CS1. On the falling edge of ICLK, the SS1 and SS3 switches open,

and the analog input is sampled on CS1. Similarly, when ICLK

is low, the analog input voltage is connected to CS2. On the

rising edge of ICLK, the SS2 and SS4 switches open, and the

analog input is sampled on CS2.

Capacitor CPA, Capacitor CPB1, and Capacitor CPB2 represent

parasitic capacitances that include the junction capacitances

associated with the MOS switches.

Table 11. Equivalent Component Values

Mode

CS1

CS2

CPA

Normal

51 pF 51 pF 12 pF

Low Power

13 pF 13 pF 12 pF

CPB1/CPB2

20 pF

5 pF

USING THE AD7763

Following is the recommended sequence for powering up and

using the AD7763.

1. Apply power.

2. Start clock oscillator, applying MCLK.

3. Take RESET low for a minimum of 1 MCLK cycle.

4. Wait a minimum of 2 MCLK cycles after RESET has been

released.

5. Write to Control Register 2 to power up the ADC and the

differential amplifier, as required.

6. Write to Control Register 1 to set up the output data rate.

7. In circumstances where multiple parts are being

synchronized, a SYNC pulse must be applied to the parts;

otherwise, no SYNC pulse is required.

AD7763

The following are conditions for applying the SYNC pulse:

• The issuing of a SYNC pulse to the part must not coincide

with a write to the part.

• The SYNC pulse should be applied a minimum

of 2.5 ICLK cycles after the FSI signal for the previous write

to the part has returned to logic high.

• Ensure that the SYNC pulse is taken low for a minimum of

2.5 ICLK cycles.

Data can now be read from the part using the default filter,

offset, gain, and overrange threshold values. The conversion

data read is not valid, however, until the settling time of the

filter has passed. When this has occurred, the DVALID bit read

is set, indicating that the data is indeed valid.

The user can then download a user-defined filter, if required

(see Downloading a User-Defined Filter). Values for gain, offset,

and overrange threshold registers can also be written or read at

this stage.

BIAS RESISTOR SELECTION

The AD7763 requires a resistor to be connected between the

RBIAS pin and AGND. The value for this resistor is dependent on

the reference voltage being applied to the device. The resistor

value should be selected to give a current of 25 µA through the

resistor to ground. For a 2.5 V reference voltage, the correct

resistor value is 100 kΩ; for a 4.096 V reference voltage, the

correct resistor value is 160 kΩ.

Rev. B | Page 21 of 32

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