EVAL-AD7763EB View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD7763EB

24-Bit, 625 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers, Serial Interface

Analog Devices 

Prev 21 22 23 24 25 26 27 28 29 30 Next

AD7763

Data Sheet

STATUS REGISTER (READ ONLY)

MSB

LSB

PART 1 PART 0 DIE 2 DIE 1 DIE 0 0 LPWR OVR DL_OK FILTER_OK UFILTER BYP F3 1 DEC2 DEC1 DEC0

Table 19.

Bit

Mnemonic

15,14 PART[1:0]

13 to 11 DIE[2:0]

10

0

9

LPWR

8

OVR

7

DL_OK

6

FILTER_OK

5

4

3

2 to 0

UFILTER

BYP F3

1

DEC[2:0]

Comment

Part Number. These bits are constant for the AD7763.

Die Number. These bits reflect the current AD7763 die number for identification purposes within a system.

0 must be written to this bit.

Low Power. If the AD7763 is operating in low power mode, this bit is set to 1.

If the current analog input exceeds the current overrange threshold, this bit is set.

When downloading a user filter to the AD7763, a checksum is generated. This checksum is compared to

the one downloaded following the coefficients. If these checksums agree, this bit is set.

When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through

the filter. This generated checksum is compared to the one downloaded. If they match, this bit is set.

If a user-defined filter is in use, this bit is set.

Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.

1 must be written to this bit.

Decimation Rate. These bits correspond to the bits set in Control Register 1.

OFFSET REGISTER—ADDRESS 0X003

Non Bit-Mapped, Default Value 0x0000

The offset register uses twos complement notation and is scaled so

that 0x7FFF (maximum positive value) and 0x8000 (maximum

negative value) correspond to an offset of +0.390625% and

−0.390625%, respectively. Offset correction is applied after any gain

correction. Using the default gain value of 1.25 and assuming a

reference voltage of 4.096 V, the offset correction range is

approximately ±25 mV.

GAIN REGISTER—ADDRESS 0X004

Non Bit-Mapped, Default Value 0xA000

The gain register is scaled so that 0x8000 corresponds to a gain

of 1.0. The default value of this register is 1.25 (0xA000). This

gives a full-scale digital output when the input is at 80% of VREF.

This ties in with the maximum analog input range of ±80% of

VREF p-p.

OVERRANGE REGISTER—ADDRESS 0X005

Non Bit-Mapped, Default Value 0xCCCC

The overrange register value is compared with the output of the

first decimation filter to obtain an overload indication with

minimum propagation delay. This is prior to any gain scaling or

offset adjustment. The default value is 0xCCCC, which

corresponds to 80% of VREF (the maximum permitted analog

input voltage). Assuming VREF = 4.096 V, the bit is then set when

the input voltage exceeds approximately 6.55 V p-p differential.

Note that the overrange bit is also set immediately if the analog

input voltage exceeds 100% of VREF for more than 4 consecutive

samples at the modulator rate.

Rev. B | Page 28 of 32

Share Link: