EVAL-AD7851CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7851CB' PDF : 36 Pages View PDF
AD7851
Mode 2 (3-Wire SPI/QSPI Interface Mode)
Default Interface Mode
Figure 35 shows the timing diagram for Interface Mode 2 which
is the SPI/QSPI interface mode. Here the SYNC input is active
low and may be pulsed or tied permanently low. If SYNC is
permanently low, 16 clock pulses must be applied to the SCLK
pin for the part to operate correctly, and with a pulsed SYNC
input a continuous SCLK may be applied provided SYNC is
low for only 16 SCLK cycles. In Figure 35, the SYNC going
low disables the three-state on the DOUT pin. The first falling
edge of the SCLK after the SYNC going low clocks out the first
leading zero on the DOUT pin. The DOUT pin is three-stated
again a time t12 after the SYNC goes high. With the DIN pin,
the data input has to be set up a time t7 before the SCLK rising
edge as the part samples the input data on the SCLK rising edge
in this case. The POLARITY pin may be used to change the
SCLK edge which the data is sampled on and clocked out on. If
resetting the interface is required, the SYNC must be taken high
and then low.
Mode 3 (QSPI Interface Mode)
Figure 36 shows the timing diagram for Interface Mode 3. In
this mode, the DSP is the master and the part is the slave. Here
the SYNC input is edge triggered from high to low, and the 16
clock pulses are counted from this edge. Because the clock
pulses are counted internally, the SYNC signal does not have to
go high after the 16th SCLK rising edge as shown by the dotted
SYNC line. Thus a frame sync that gives a high pulse of one
SCLK cycle minimum duration at the beginning of the read/
write operation may be used. The rising edge of SYNC enables
the three-state on the DOUT pin. The falling edge of SYNC
disables the three-state on the DOUT pin, and data is clocked
out on the falling edge of SCLK. Once SYNC goes high, the
three-state on the DOUT pin is enabled. The data input is
sampled on the rising edge of SCLK and thus has to be valid a
time t7 before this rising edge. The POLARITY pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC must be taken high and then low.
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
t3 = –0.4 tCLKIN MIN (NONCONTINUOUS SCLK) ±0.4 tSCLK MIN/MAX (CONTINUOUS SCLK),
t6 = 45ns MAX, t7 = 30ns MIN, t8 = 20ns MIN, t11 = 30ns MIN (NONCONTINUOUS SCLK),
30/0.4 tSCLK = ns MIN/MAX (CONTINUOUS SCLK)
t3
SCLK (I/P)
1
t5
DOUT (O/P) THREE-STATE
t6
DB15
t7
t8
DIN (I/P)
DB15
t9
2
3
t10
DB14
DB13
4
DB12
5
t6
DB11
DB14
DB13
DB12
DB11
6
DB10
t8
DB10
t11
16
DB0
t12
THREE-STATE
DB0
Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output, and SYNC Input
(SM1 = SM2 = 0)
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
t3 = –0.4 tCLKIN MIN (NONCONTINUOUS SCLK) ±0.4 tSCLK MIN/MAX (CONTINUOUS SCLK),
t6 = 45ns MAX, t7 = 30ns MIN, t8 = 20ns MIN, t11 = 30ns MIN
t3
SCLK (I/P)
1
t5
DOUT (O/P) THREE-STATE
t6
DB15
t7
t8
DIN (I/P)
DB15
t9
2
3
t10
DB14
DB13
DB14
DB13
4
DB12
DB12
5
t6
DB11
DB11
6
DB10
t8
DB10
t11
16
DB0
t12
THREE-STATE
DB0
Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1)
–26–
REV. B
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