AD7851
If the user has control of the CONVST pin but does not want to
exercise it for every conversion, the control register may be used
to start a conversion. Setting the CONVST bit in the control
register to 1 starts a conversion. If the user does not have con-
trol of the CONVST pin, a conversion should not be initiated
by writing to the control register. The reason for this is that the
user may get locked out and not be able to perform any further
write/read operations. When a conversion is started by writing to
the control register, the SYNC goes low and read/write opera-
tions take place while the conversion is in progress. However,
once the conversion is complete, there is no way of writing to
the part unless the CONVST pin is exercised. The CONVST
signal triggers the SYNC signal low which allows read/write
operations to take place. SYNC must be low to perform read/
write operations. The SYNC is triggered low by the CONVST
signal rising edge or by setting the CONVST bit in the control
register to 1. Therefore, if there is not full control of the
CONVST pin, the user may become locked out.
CONFIGURING THE AD7851
AD7851 as a Read-Only ADC
The AD7851 contains 14 on-chip registers that can be accessed
via the serial interface. In the majority of applications, it will not
be necessary to access all of these registers. Figure 40 outlines the
sequence used to configure the AD7851 as a read-only ADC. In
this case, there is no writing to the on-chip registers and only the
conversion result data is read from the part. Interface Mode 1
cannot be used in this case as it is necessary to write to the con-
trol register to set Interface Mode 1. Here the CLKIN signal is
applied directly after power-on; the CLKIN signal must be
present to allow the part to perform a calibration. This automatic
calibration will be completed approximately 42 ms after the
AD7851 has powered up (6 MHz CLK).
START
DIN CONNECTED TO DGND
POWER ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
SERIAL
4, 5
INTERFACE
MODE
?
2, 3
PULSE CONVST PIN
PULSE CONVST PIN
READ
DATA
DURING
CONVERSION
?
YES
SYNC AUTOMATICALLY GOES LOW
AFTER CONVST RISING EDGE
NO
WAIT FOR BUSY SIGNAL
TO GO LOW
WAIT APPROXIMATELY 200ns
AFTER CONVST RISING EDGE
APPLY SYNC (IF REQUIRED), SCLK, AND READ
CONVERSION RESULT ON DOUT PIN
SCLK AUTOMATICALLY ACTIVE, READ
CONVERSION RESULT ON DOUT PIN
Figure 40. Flowchart for Setting Up and Reading from the AD7851
–28–
REV. B