EVAL-AD7879EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7879EBZ' PDF : 36 Pages View PDF
AD7879/AD7889
Data Sheet
CONTROL REGISTERS
CONTROL REGISTER 1
Control Register 1 (Address 0x01) contains the ADC channel
address and the ADC mode bits. It sets the acquisition time and
the timer. It also contains a bit to disable the pen interrupt.
Control Register 1 must always be the last register programmed
prior to starting conversions. Its power-on default value is 0x0000.
To change any parameter after conversion has begun, the device
must first be put into ADC Mode 00. Make the changes, and
then reprogram Control Register 1, ensuring that it is always
the last register programmed before conversions begin.
Timer (Control Register 1, Bits[7:0])
The TMR bits in Control Register 1 set the conversion interval
timer, which enables the ADC to perform a conversion sequence at
regular intervals from 550 μs (00000001) up to 9.440 ms
(11111111) in increments of 35 μs (see Table 18). The default
value of these bits is 00000000, which enables the ADC to
perform one conversion only.
In slave mode, the timer starts as soon as the conversion sequence
is finished. In master mode, the timer starts at the end of a conver-
sion sequence only if the screen remains touched. If the touch is
released at any stage, the timer stops. The next time that the
screen is touched, a conversion sequence begins immediately.
Table 18. Timer Selection
TMR[7:0]
Conversion Interval
00000000 Convert one time only (default)
00000001 Every 550 μs
00000010 Every 585 μs
00000011 Every 620 μs
…
…
11111101 Every 9.370 ms
11111110 Every 9.405 ms
11111111 Every 9.440 ms
Acquisition Time (Control Register 1, Bits[9:8])
The ACQ bits in Control Register 1 allow the selection of acquisi-
tion times for the ADC of 2 μs (default), 4 μs, 8 μs, or 16 μs. The
user can program the ADC with an acquisition time suitable for
the type of signal being sampled. For example, signals with large
RC time constants can require longer acquisition times.
Table 19. Acquisition Time Selection
ACQ1
ACQ0
Acquisition Time
0
0
4 clock periods (2 μs)
0
1
8 clock periods (4 μs)
1
0
16 clock periods (8 μs)
1
1
32 clock periods (16 μs)
ADC Mode (Control Register 1, Bits[11:10])
The mode bits select the operating mode of the ADC. The
AD7879/AD7889 have three operating modes. These modes are
selected by writing to the mode bits in Control Register 1. If the
mode bits are set to 00, no conversion is performed.
Table 20. Mode Selection
ADC
ADC
MODE1 MODE0 Function
0
0
Do not convert (default)
0
1
Single-channel conversion; the device is
in slave mode
1
0
Sequence 0; the device is in slave mode
1
1
Sequence 1; the device is in master mode
If the mode bits are set to 01, a single conversion is performed
on the channel selected by writing to the channel bits of Control
Register 1 (Bits[14:12]). At the end of the conversion, if the TMR
bits in Control Register 1 are set to 00000000, the mode bits
revert to 00 and the ADC returns to no convert mode until a
new conversion is initiated by the host. Setting the TMR bits to
a value other than 00000000 causes the conversion to be repeated.
The AD7879/AD7889 can also be programmed to automatically
convert a sequence of selected channels. The two modes for this
type of conversion are slave mode and master mode.
For slave mode operation, the channels to be digitized are selected
by setting the corresponding bits in Control Register 3. Conversion
is initiated by writing 10 to the mode bits of Control Register 1.
The ADC then digitizes the selected channels and stores the results
in the corresponding result registers. At the end of the conversion,
if the TMR bits in Control Register 1 are set to 00000000, the
mode bits revert to 00 and the ADC returns to no convert mode
until a new conversion is initiated by the host. Setting the TMR
bits to a value other than 00000000 causes the conversion
sequence to be repeated.
15
0
DISABLE
PENIRQ
CHNL
ADD2
CHNL
ADD1
CHNL
ADD0
ADC
MODE1
ADC
MODE0
ACQ1
ACQ0
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Figure 30. Control Register 1
Rev. D | Page 26 of 40
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