EVAL-AD7879EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7879EBZ' PDF : 36 Pages View PDF
AD7879/AD7889
CONTROL REGISTER 3
Control Register 3 (Address 0x03) includes the interrupt
register (Bits[15:8]) and the sequencer bits (Bits[7:0]).
Sequencer (Control Register 3, Bits[7:0])
The sequencer bits control which channels are converted during
a conversion sequence in both slave mode and master mode.
To include a measurement in a sequence, the relevant bit must
be set in the sequence. Setting Bit 7 includes a measurement on
the X+ channel (Y position). Setting Bit 6 includes a measure-
ment on the Y+ channel (X position), and so on (see Table 14).
Figure 34 illustrates the correspondence between the bits in
Control Register 3 and the various measurements. Bit 0 is
not used.
01
SINGLE
CONVERSION
00
IDLE
ADC MODE?
10
SLAVE MODE
CONVERSION
SEQUENCE
YES TIMER = 00?
NO
START TIMER
WAIT FOR TIMER
11
MASTER MODE
WAIT FOR
FIRST TOUCH
CONVERSION
SEQUENCE
SCREEN
NO
TOUCHED?
YES
YES
TIMER = 00?
NO
START TIMER
WAIT FOR TIMER
Data Sheet
START OF
CONVERSION
SEQUENCE
SET CHANNEL
FCD
YES
FCD
REQ’D?
NO
WAIT FOR
ACQUISITION
ACQ
YES
RANK NEW
DATA
(WAIT tSORT)
NO
MEDIAN
# OF SAMPLES
TAKEN?1
CONVERT DATA
YES
MAV FILTER
ENABLED
?
NO
AVERAGE DATA
TRANSFER DATA
TO REGISTERS
SET ALERT AND
INTERRUPT
YES
OUT-OF-
LIMIT?
NO
END OF
NO
SEQUENCE
?
YES
1MEDIAN # MEANS MEDIAN
FILTER SIZE.
FCD
Figure 33. Conversion Sequence
SCREEN
NO
TOUCHED?
YES
Figure 32. Conversion Modes
15
TEMP
MASK
AUX/
VBAT
MASK
INT GPIO
MODE ALERT
AUX/
VBAT
LOW
AUX/
VBAT
HIGH
TEMP
LOW
TEMP
HIGH
X+
Y+
Z1
Figure 34. Control Register 3
0
Z2
AUX
VBAT
TEMP
NOT
USED
Rev. D | Page 30 of 40
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