EVAL-AD7980SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7980SDZ' PDF : 29 Pages View PDF
AD7980
Data Sheet
3-WIRE CS MODE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 31, and the corresponding timing is given in
Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7980 enters the acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate provided that it has
an acceptable hold time. After the 16th SCK falling edge or
when CNV goes high, whichever is earlier, SDO returns to high
impedance.
CNV
VIO
SDI AD7980 SDO
SCK
CONVERT
DIGITAL HOST
DATA IN
CLK
SDI = 1
CNV
AQUISITION
SCK
SDO
tCNVH
Figure 31. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
tCYC
tCONV
CONVERSION
tACQ
AQUISITION
tSCKL
tSCK
1
2
3
14
15
16
tHSDO
tEN
tDSDO
tSCKH
tDIS
D15
D14
D13
D1
D0
Figure 32. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. F | Page 18 of 26
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