EVAL-AD7983SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7983SDZ' PDF : 24 Pages View PDF
Data Sheet
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input.
The connection diagram is shown in Figure 27, and the
corresponding timing is given in Figure 28.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data read back controlled by the
digital host. The AD7983 then enters the acquisition phase and
goes into standby mode. The data bits are then clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
AD7983
If multiple AD7983s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended that this contention be
kept as short as possible to limit extra power dissipation.
CONVERT
CNV
VIO
DIGITAL HOST
VIO
SDI AD7983 SDO
47kΩ
DATA IN
SCK
IRQ
CLK
Figure 27. CS Mode, 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
CNV
ACQUISITION
tCNVH
tCONV
CONVERSION
SCK
SDO
tCYC
tACQ
ACQUISITION
tSCKL
tSCK
1
2
3
15
16
17
tHSDO
tSCKH
tDSDO
tDIS
D15
D14
D1
D0
Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 19 of 25
Share Link: 
