EVAL-AD7983SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7983SDZ' PDF : 24 Pages View PDF
AD7983
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7983s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7983s is shown in
Figure 29, and the corresponding timing is given in Figure 30.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback (if SDI and CNV are low,
SDO is driven low). Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
multiplexers, but SDI must be returned high before the
minimum conversion time elapses and then held high for the
maximum conversion time to avoid the generation of the busy
signal indicator.
Data Sheet
When the conversion is complete, the AD7983 enters the
acquisition phase and goes into standby mode. Each ADC
result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7983 can be read.
CNV
SDI AD7983 SDO
SCK
CNV
SDI AD7983 SDO
SCK
CS2
CS1
CONVERT
DIGITAL HOST
DATA IN
CLK
Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
CNV
ACQUISITION
tCONV
CONVERSION
tSSDICNV
SDI(CS1)
tHSDICNV
tCYC
tACQ
ACQUISITION
SDI(CS2)
SCK
SDO
tSCK
tSCKL
1
2
3
14
15
16
tHSDO
tSCKH
tEN
tDSDO
D15 D14 D13
D1
D0
17
18
30
D15 D14
Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
31
32
tDIS
D1
D0
Rev. C | Page 20 of 25
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