EVAL-AD7985FMCZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7985FMCZ' PDF : 28 Pages View PDF
Data Sheet
AD7985
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7985 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
Figure 27.
With SDI tied to VIO, a rising edge on CNV initiates a con-
version, selects CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues until completion,
irrespective of the state of CNV.
CNV
VIO
SDI AD7985 SDO
This can be useful, for example, to bring CNV low to select
other SPI devices, such as analog multiplexers; however, CNV
must be returned high before the minimum conversion time
elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
When the conversion is complete, the AD7985 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
that it has an acceptable hold time. After the 16th SCK falling edge
or when CNV goes high (whichever occurs first), SDO returns to
high impedance.
CONVERT
DIGITAL HOST
DATA IN
SDI = 1
CNV
ACQUISITION
(n – 1)
SCK
SDO
SCK
CLK
Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
tDATA
>tCONV
tCONV
tCYC
tCONV
tDATA
tCNVH
tACQ
CONVERSION (n – 1)
(I/O QUIET
TIME)
ACQUISITION (n)
(I/O QUIET
TIME)
CONVERSION (n)
14 15 16
tEN
210
tDIS END DATA (n – 2)
tDIS
12
tHSDO
tEN
tDSDO
15 14 13
BEGIN DATA (n – 1)
tQUIET
14 15 16
tSCK
21 0
tDIS END DATA (n – 1)
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
(I/O QUIET ACQUISITION
TIME)
(n + 1)
tDIS
Rev. C | Page 19 of 28
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