EVAL-ADE7759E View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADE7759E' PDF : 32 Pages View PDF
ADE7759
DB7
W/R
DB6
0
Table V. Communications Register
DB5
0
DB4
A4
DB3
A3
DB2
A2
DB1
A1
DB0
A0
Bit
Location
0 to 4
5 to 6
7
Bit
Mnemonic
A0 to A4
RESERVED
W/R
Description
The five LSBs of the Communications register specify the register for the data transfer operation.
Table III lists the address of each ADE7759 on-chip register.
These bits are unused and should be set to zero.
When this bit is a Logic 1, the data transfer operation immediately following the write to the
Communications register will be interpreted as a write to the ADE7759. When this bit is a
Logic 0 the data transfer operation immediately following the write to the Communications
register will be interpreted as a read operation.
Mode Register (06H)
The ADE7759 functionality is configured by writing to the MODE register—see Figure 45. Table VI summarizes the functionality of
each bit in the Mode Register.
Table VI. Mode Register
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
12, 11
14, 13
15
Bit
Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
TEMPSEL
SWRST
CYCMODE
DISCH1
DISCH2
SWAP
DTRT1, 0
WAVSEL1, 0
TEST1
Description
The HFP (high-pass filter) in Channel 1 is disabled when this bit is set.
The LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
The Frequency output CF is disabled when this bit is set.
The line voltage sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both ADE7759s A/D converters can be turned off. In normal opera-
tion, this bit should be left at Logic 0. All digital functionality can be stopped by suspending the
clock signal at CLKIN pin.
The temperature conversion starts when this bit is set to 1. This bit is automatically reset to
0 when the temperature conversion is finished.
Software Chip Reset. A data transfer should not take place to the ADE7759 for at least 18 µs after
a software reset.
Setting this bit to Logic 1, places the chip in Line Cycle Energy Accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the
analog inputs V1P and V1N are connected to ADC 2.
These bits are used to select the Waveform register update rate.
DTRT 1 DTRT0 Update Rate
0
0
27.9 kSPS (CLKIN/128)
0
1
14 kSPS (CLKIN/256)
1
0
7 kSPS (CLKIN/512)
1
1
3.5 kSPS (CLKIN/1024)
These bits are used to select the source of the sampled data for the Waveform register.
WAVSEL1, 0 Length Source
00
24 bits Active Power Signal (output of LPF2)
01
40 bits Channel 1 and Channel 2
10
24 bits Channel 1
11
24 bits Channel 2
Writing a Logic 1 to this bit position places the ADE7759 in test mode. This is intended for
factory testing only and should be left at 0.
–30–
REV. 0
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