EVAL-ADE7880EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADE7880EBZ' PDF : 107 Pages View PDF
ADE7880
PGA1 BITS
GAIN[2:0]
REFERENCE
×1, ×2, ×4, ×8, ×16
IAP
VIN
PGA1
IAN
ADC
VIN
+0.5V/GAIN
0V
–0.5V/GAIN
ANALOG INPUT RANGE
Data Sheet
DSP
INTEN BIT
CONFIG[0]
HPFEN BIT
CONFIG3[0] DIGITAL
INTEGRATOR
AIGAIN[23:0]
HPF
ZX DETECTION
LPF1
0x514791 =
CURRENT PEAK,
+5,326,737
OVERCURRENT
DETECT
0V
CURRENT RMS (IRMS)
CALCULATION
ZX SIGNAL
DATA RANGE
IAWV WAVEFORM
SAMPLE REGISTER
TOTAL/FUNDAMENTAL
ACTIVE AND REACTIVE
POWER CALCULATION
0xAEB86F =
–5,326,737
0x514791 =
+5,326,737
CURRENT CHANNEL
DATA RANGE
0V
0xAEB86F =
–5,326,737
Figure 42. Current Channel Signal Path
PGA2 BITS
GAIN[5:3]
REFERENCE
×1, ×2, ×4, ×8, ×16
IAP
DSP
HPFEN BIT
CONFIG3[0]
ININTEN BIT
CONFIG3[3]
DIGITAL
NIGAIN[23:0]
INTEGRATOR
CURRENT RMS (IRMS)
CALCULATION
VIN
PGA2
IAN
ADC
HPF
INWV WAVEFORM
SAMPLE REGISTER
Figure 43. Neutral Current Signal Path
Current Waveform Gain Registers
There is a multiplier in the signal path of each phase and neutral
current. The current waveform can be changed by ±100% by
writing a corresponding twos complement number to the 24-bit
signed current waveform gain registers (AIGAIN, BIGAIN,
CIGAIN, and NIGAIN). For example, if 0x400000 is written to
those registers, the ADC output is scaled up by 50%. To scale
the input by −50%, write 0xC00000 to the registers. Equation 4
describes mathematically the function of the current waveform
gain registers.
Current Waveform =
ADC Output
×
1
+
Content
of
Current
223
Gain Register
(4)
Changing the content of the AIGAIN, BIGAIN, CIGAIN, or
INGAIN registers affects all calculations based on its current;
that is, it affects the corresponding phase active/reactive/
apparent energy and current rms calculation. In addition,
waveform samples scale accordingly.
31
28 27
0000
24 23
0
24-BIT NUMBER
BITS[27:24] ARE BIT 23 IS A SIGN BIT
EQUAL TO BIT 23
Figure 44. 24-Bit xIGAIN Transmitted as 32-Bit Words
Current Channel HPF
The ADC outputs can contain a dc offset. This offset can create
errors in power and rms calculations. High-pass filters (HPFs)
are placed in the signal path of the phase and neutral currents
and of the phase voltages. If enabled, the HPF eliminates any dc
offset on the current channel. All filters are implemented in the
DSP and, by default, they are all enabled: Bit 0 (HPFEN) of the
CONFIG3[7:0] register is set to 1. All filters are disabled by
setting Bit 0 (HPFEN) to 0.
Note that the serial ports of the ADE7880 work on 32-, 16-, or
8-bit words, and the DSP works on 28 bits. The 24-bit AIGAIN,
BIGAIN, CIGAIN, and NIGAIN registers are accessed as 32-bit
registers with the four most significant bits (MSBs) padded with
0s and sign extended to 28 bits. See Figure 44 for details.
Rev. C | Page 28 of 107
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