EVAL-ADE7880EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADE7880EBZ' PDF : 107 Pages View PDF
Data Sheet
Voltage Waveform Gain Registers
There is a multiplier in the signal path of each phase voltage.
The voltage waveform can be changed by ±100% by writing
a corresponding twos complement number to the 24-bit signed
voltage waveform gain registers (AVGAIN, BVGAIN, and
CVGAIN). For example, if 0x400000 is written to those registers,
the ADC output is scaled up by 50%. To scale the input by −50%,
write 0xC00000 to the registers. Equation 5 describes mathe-
matically the function of the current waveform gain registers.
Voltage Waveform =
ADC
Output
×
1
+
Content
of
Voltage
223
Gain
Register
(5)
Changing the content of the AVGAIN, BVGAIN, and CVGAIN
registers affects all calculations based on its voltage; that is, it
affects the corresponding phase active/reactive/apparent energy
and voltage rms calculation. In addition, waveform samples are
scaled accordingly.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words,
and the DSP works on 28 bits. As presented in Figure 44, the
AVGAIN, BVGAIN, and CVGAIN registers are accessed as
32-bit registers with four MSBs padded with 0s and sign
extended to 28 bits.
Voltage Channel HPF
As explained in the Current Channel HPF section, the ADC
outputs can contain a dc offset that can create errors in power
and rms calculations. HPFs are placed in the signal path of the
phase voltages, similar to the ones in the current channels. Bit 0
(HPFEN) of CONFIG3 register can enable or disable the filters.
See the Current Channel HPF section for more details.
Voltage Channel Sampling
The waveform samples of the voltage channel are taken at the
output of HPF and stored into VAWV, VBWV, and VCWV
24-bit signed registers at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the VAWV,
VBWV, and VCWV registers are available to be read using the
I2C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
register enables an interrupt to be set when the DREADY flag is
set. See the Digital Signal Processor section for more details on
Bit DREADY.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to registers presented in Figure 45, the VAWV, VBWV,
and VCWV 24-bit signed registers are transmitted sign
extended to 32 bits.
The ADE7880 contains an HSDC port especially designed to
provide fast access to the waveform sample registers. See the
HSDC Interface section for more details.
ADE7880
CHANGING PHASE VOLTAGE DATA PATH
The ADE7880 can direct one phase voltage input to the
computational data path of another phase. For example, Phase A
voltage can be introduced in the Phase B computational data path,
which means all powers computed by the ADE7880 in Phase B
are based on Phase A voltage and Phase B current.
Bits[9:8] (VTOIA[1:0]) of the CONFIG register manage which
phase voltage is directed to the Phase A computational data path. If
VTOIA[1:0] = 00 (default value), the Phase A voltage is directed
to the Phase A computational data path. If VTOIA[1:0] = 01,
the Phase B voltage is directed to the Phase A computational
data path. If VTOIA[1:0] = 10, the Phase C voltage is directed
to the Phase A computational data path. If VTOIA[1:0] = 11,
the ADE7880 behaves as if VTOIA[1:0] = 00.
Bits[11:10] (VTOIB[1:0]) of the CONFIG register manage
which phase voltage is directed to the Phase B computational
data path. If VTOIB[1:0] = 00 (default value), the Phase B
voltage is directed to the Phase B computational data path.
If VTOIB[1:0] = 01, the Phase C voltage is directed to the
Phase B computational data path. If VTOIB[1:0] = 10, the Phase A
voltage is directed to the Phase B computational data path. If
VTOIB[1:0] = 11, the ADE7880 behaves as if VTOIB[1:0] = 00.
Bits[13:12] (VTOIC[1:0]) of the CONFIG register manage
which phase voltage is directed to the Phase C computational
data path. If VTOIC[1:0] = 00 (default value), the Phase C
voltage is directed to the Phase C computational data path, if
VTOIC[1:0] = 01, the Phase A voltage is directed to the Phase C
computational data path. If VTOIC[1:0] = 10, the Phase B
voltage is directed to the Phase C computational data path. If
VTOIC[1:0] = 11, the ADE7880 behaves as if VTOIC[1:0] = 00.
IA
APHCAL
VA
IB
PHASE A
COMPUTATIONAL
DATAPATH
VTOIA[1:0] = 10,
PHASE A VOLTAGE
DIRECTED
TO PHASE B
BPHCAL
VB
IC
PHASE B
COMPUTATIONAL
DATAPATH
VTOIB[1:0] = 10,
PHASE B VOLTAGE
DIRECTED
TO PHASE C
CPHCAL
VC
PHASE C
COMPUTATIONAL
DATAPATH
VTOIC[1:0] = 10,
PHASE C VOLTAGE
DIRECTED
TO PHASE A
Figure 51. Phase Voltages Used in Different Data Paths
Figure 51 presents the case in which the Phase A voltage is used
in the Phase B data path, the Phase B voltage is used in the Phase C
data path, and the Phase C voltage is used in the Phase A data path.
Rev. C | Page 31 of 107
Share Link: 
