INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 19 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these compara-
tors have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 6.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program how much above the
UV threshold the input must rise again before a UV fault is
deasserted. Similarly, the user can program how much below
the OV threshold an input must fall again before an OV fault is
deasserted.
The hysteresis figure is given by
VHYST = VR × NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
allowing the user to remove any spurious transitions such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD compara-
tors. The glitch filter timeout is programmable up to 100 μs.
For example, when the glitch filter timeout is 100 μs, any pulses
appearing on the input of the glitch filter block that are less than
100 μs in duration are prevented from appearing on the output
of the glitch filter block. Any input pulse that is longer than
100 μs appears on the output of the glitch filter block. The
output is delayed with respect to the input by 100 μs. The
filtering process is shown in Figure 20.
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
PROGRAMMED
TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
T0
TGF
INPUT
T0
TGF
OUTPUT
OUTPUT
T0
TGF
T0
TGF
Figure 20. Input Glitch Filter Function
ADM1067
SUPPLY SUPERVISION WITH VXn INPUTS
The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected
as an analog (SFD) input, the VXn pins have very similar
functionality to the VH and VPn pins. The major difference
is that the VXn pins have only one input range: 0.573 V to
1.375 V. Therefore, these inputs can directly supervise only the
very low supplies. However, the input impedance of the VXn pins
is high, allowing an external resistor divide network to be
connected to the pin. Thus, any supply can be potentially
divided down into the input range of the VXn pin and be
supervised. This enables the ADM1067 to monitor other
supplies such as +24 V, +48 V, and −5 V.
An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi-
cated analog inputs, VPn and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is
mapped to VH. In this case, these SFDs can be viewed as a
secondary or warning SFD.
The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be
generated on a single supply using only one pin. For example, if
VP1 is set to output a fault if a 3.3 V supply drops to 3.0 V, VX1
can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
OR’ed together and fed into the sequencing engine (SE),
allowing warnings to generate interrupts on the PDOs.
Therefore, in this example, if the supply drops to 3.1 V, a
warning is generated, and remedial action can be taken before
the supply drops out of tolerance.
VXn PINS AS DIGITAL INPUTS
As mentioned in the Supply Supervision with VXn Inputs
section, the VXn input pins on the ADM1067 have dual func-
tionality. The second function is as a digital input to the device.
Therefore, the ADM1067 can be configured for up to five digital
inputs. These inputs are TTL-/CMOS- compatible. Standard
logic signals can be applied to the pins: RESET from reset
generators, PWRGD signals, fault flags, manual resets, and so
on. These signals are available as inputs to the SE, and therefore,
can be used to control the status of the PDOs. The inputs can be
configured to detect either a change in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, once the logic transition is detected, a pulse of
programmable width is output from the digital block. The
width is programmable from 0 μs to 100 μs.
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