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EVAL-ADM1067LFEB View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
EVAL-ADM1067LFEB
ADI
Analog Devices ADI
'EVAL-ADM1067LFEB' PDF : 32 Pages View PDF
ADM1067
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the sequencing engine (SE). Figure 24 shows how the simple
building block of a single SE state can be used to build a power-
up sequence for a 3-supply system.
Table 8 lists the PDO outputs for each state in the same SE
implementation. In this system, the presence of a good 5 V
supply on VP1 and the VX1 pin held low are the triggers
required for a power-up sequence to start. The sequence next
intends to turn on the 3.3 V supply, and then the 2.5 V supply
(assuming successful turn-on of the 3.3 V supply). Once all
three supplies are good, the PWRGD state is entered, where the
SE remains until a fault occurs on one of the three supplies or
until it is instructed to go through a power-down sequence by
VX1 going high.
SEQUENCE
STATES
IDLE1
VX1 = 0
IDLE2
MONITOR FAULT
STATES
VP1 = 1
EN3V3
VP1 = 0
10ms
TIMEOUT
STATES
VP2 = 1
EN2V5
(VP1 + VP2) = 0
20ms
VP3 = 1
DIS3V3
VX1 = 1
(VP1 + VP2 + VP3) = 0
FSEL1
(VP1 +
VP2) = 0
PWRGD
DIS2V5
VP2 = 0
VX1 = 1
VX1 = 1
VP3 = 0
FSEL2
VP1 = 0
VP2 = 0
Figure 24. Sample Application Flow Diagram
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections describe the
individual blocks and use the sample application in Figure 24 to
demonstrate the state machine’s actions.
Sequence Detector
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state, and is most often used as the gate on successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 25 is a block diagram of
the sequence detector.
VP1
SUPPLY FAULT
DETECTION
SEQUENCE
DETECTOR
VX5
LOGIC INPUT CHANGE
OR FAULT DETECTION
TIMER
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
INVERT
SELECT
Figure 25. Sequence Detector Block Diagram
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 24, the FSEL1
and FSEL2 states first identify which of the VP1, VP2, or VP3
pins has faulted, and then they take the appropriate action.
Monitoring Fault Detector
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the PWRGD state, where the monitor block
indicates that a failure on one or more of the VP1, VP2, or VP3
inputs has occurred.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the user needs to react
as quickly as possible. Some latency occurs when moving out of
this state, however, because it takes a finite amount of time
(~20 μs) for the state configuration to download from EEPROM
into the SE. Figure 26 is a block diagram of the monitoring fault
detector.
Table 8. PDO Outputs for Each State
PDO Outputs
IDLE1 IDLE2
PDO1 = 3V3ON
0
0
PDO2 = 2V5ON
0
0
PDO3 = FAULT
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
Rev. B | Page 20 of 32
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
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